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Recent content by AdvaRes

  1. AdvaRes

    CDF parameter passing problem

    Hi dick_freebird, Thank you for prompt reply. For the inverter, pPar("wp"), pPar("wn") , pPar("lp") and pPar("ln") were defined. Using the CDF editor the these parameters were assigned some default values. I also added labels for the symbol to display these properties. I did so for the top...
  2. AdvaRes

    CDF parameter passing problem

    Hi all, I'm finding difficulty to pass CDF parameters from a lower level cell to higher level cell in a circuit. Its the first time that I try to use CDF parameter in a hierarchical design. I designed an inverter with wp, wn, lp and ln (Width of PMOS and NMOS + length of PMOS and NMOS) as CDF...
  3. AdvaRes

    the problem about pll spur

    Please provide more detail on your circuit pdf, cp
  4. AdvaRes

    555 timer frequency problem

    Hi, You can find a lot of tools for you calculation on the www: http://www.ohmslawcalculator.com/555_astable.php http://www.buildcircuit.com/free-555-timer-simulator-for-electronics-beginners/ Advares
  5. AdvaRes

    HP 510 Battery Charger selection and calibration help needed

    Hi all, I recently aquired a battery for my HP 510 laptop (Reference: HP 510 HSTNN-IB45 HSTNN-C29C). It is a 5200mAh 14.8V replacement battery selected to replace the dead low capacity 2200mAh, 14.8V original battery and to provide longer autonomy. Once the new battery received, I mounted it...
  6. AdvaRes

    Text editor for VHDL on a Mac

    You can use editors like : TextWrangler, Editra, gedit, TaterEdit, Bluefish....
  7. AdvaRes

    Help installing Cadence IC 6.1 on Fedora

    Fedora remains a linux OS. The same steps are required to install cadence on linux. Search in Eda you will find a lot of answers
  8. AdvaRes

    Does the length of mos can exceed the upper limit in PDK?

    To avoid the PDK limits and to have a good moscap, fingered transistors is a nice choice.
  9. AdvaRes

    FIFO depth and full condition

    in 0.1µs (the period of the slowest clock) a single data is writen and read. So your fifo will never be full even if it was of 1 depth.
  10. AdvaRes

    QUery in transition delay after clock tree synthesis

    use synopsys tool use the set_clock_transistion command. For more detail see: Milkyway and Physical Implementation Commands p 571. www.61eda.com/code/attachment.php?aid=3438&k...t=1287224009
  11. AdvaRes

    M1_N vs NTAP and M1_P vs PTAP

    m1_n to m1_p to place the source contacts. The ntap and ptap instances provide substrate contacts for the design.
  12. AdvaRes

    Frequency Modulation Using MATLAB

    Hi, The code is correct and works fine. I even tested it with Matlab.
  13. AdvaRes

    Net work on chip graduation project

    Hi Rafale, Do you have a project or you are looking for project Idea ? NoC is a wide issue. What are the things that interrest you in NoC, Modeling ? Design ? Performance evaluation ? Benchmarcking ? Mapping ? I can't help you if you give us more details on your preferences and if possible some...
  14. AdvaRes

    why voltage is same across parallel resistors( another confusion)

    The power supply voltage remain constant and exerce no push. It is the resistance who will draw the current from the source depending on their resistance value. The current max drawn will depend on the power of your source. You have to study power supply source to understand this analogy.
  15. AdvaRes

    One cycle delay vhdl

    @TrickyDicky With all my respect Sir, we dont need a troll to comment our posts in this forum. If you are cleaver answer the question. @needhelp123 Please try this one and let me know. Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all...
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