Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by abu9022

  1. A

    is there any open source projects?

    Hi friends is there any website available for open source projects in VLSI field
  2. A

    [moved] Job Title Suggestion in VLSI field

    Hi Friends Can anyone tell me Job Title related to Digital VLSI Design
  3. A

    [moved] Job Title Suggestion in VLSI field

    Hi Friends I am looking for Entry level Position, can you suggest me type of jobs related to my coursework. Coursework:(Master) VLSI System Design, Analog IC Design, Mixed Signal Design, Computer Architecture, Computer Arithmetic, FPGA and HDL and did a Final Graduate Project in VLSI testing I...
  4. A

    Error: Illegal port association

    Hi Friends, I have the following error, can you help me Error-[ANL-UNASSO-PORT] Illegal port association leon/mcore_te.vhd, 36 TB_FUNC32 Unassociated port TE of mode IN in entity MCORE has no default value. Error-[ANL-UNASSO-PORT] Illegal port association leon/mcore_te.vhd, 36 TB_FUNC32...
  5. A

    unbound componet vhdl error

    I am still seeing the problem I am running the command ./razor_script razor_script rm -rf ./csrc rm -rf ./simv* rm -rf ./work_vcs mkdir ./work_vcs #vlogan NangateOpenCellLibrary_slow_conditional.v #vlogan gscl45nm.v vhdlan -w work leon/std_logic_signed.vhd vhdlan -w work...
  6. A

    unbound componet vhdl error

    Hi sharath, I added the file mcore_te.vhd ---------------------------------------------------------------------------- -- This file is a part of the LEON VHDL model -- Copyright (C) 1999 European Space Agency (ESA) -- -- This library is free software; you can redistribute it and/or...
  7. A

    unbound componet vhdl error

    Hi Friends Can you please help me how to solve the warning Warning-[ELW_UNBOUND] Unbound component The component instantiation '/TBLEON/TB/P0/LEON0/MCORE0' (file: /mnt/iscsi/Users/ee5113/zxv764/leon2-1.0.30-xst/leon/leon_te.vhd, line: 141) will have no effect because component 'MCORE'...
  8. A

    doubt in VHDL testbench

    Hi friends I have the Test Enable signal(TE) which should be write in VHDL, clkperiod : integer := 4; -- system clock period signal clk : std_logic := '0'; signal te : std_logic := '0'; constant ct : integer := clkperiod/2; clk is already written Can I know how to write...
  9. A

    estimated critical path coverage

    How to find estimated critical path coverage?
  10. A

    NangateOpenCellLibrary_slow_conditional.v 1662 timing violation

    Hi Friends can you help me, how to solve the following error(Timing Violation) while running VCS simulation Chronologic VCS simulator copyright 1991-2011 Contains Synopsys proprietary information. Compiler version E-2011.03-SP1; Runtime version E-2011.03-SP1; Nov 12 18:32 2014 Doing SDF...
  11. A

    INTERCONNECT wil still be annotated

    Hi Friends can you help me how to solve this warning Warning-[SDFCOM_IWSBA] INTERCONNECT will still be annotated ./leon/iu_verilog2.sdf, 1804 module: iu_verilog2, "instance: TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1.iu2" SDF Warning: INTERCONNECT from rst to U9846.A has Continuous...
  12. A

    Create a group of setup timing error

    1. How to create a group of setup timing error by reducing clock cycle time? If I reduce clock cycle time it may be go slack negative, it's correct
  13. A

    what to do "Path is unconstrained"

    Currently, I am using clk=7 ns, so i need to increase clock? for 7 ns, below is report_timing Des/Clust/Port Wire Load Model Library ------------------------------------------------ iu 5K_hvratio_1_1 NangateOpenCellLibrary Point...
  14. A

    what to do "Path is unconstrained"

    Hi Friends when I am trying the command "report_timing", I am not getting Slack, but I am getting path is unconstrained can you tell me How to solve Path is unconstrained Below is my script file can you check I need to add anything ################################################# # list of...
  15. A

    How to solve Hold Time Violation

    Hi Friends, I dont know How to solve the Hold time violation, can you help me Error: "NangateOpenCellLibrary_slow_conditional.v", 1614: Timing violation in \TBLEON.TB.P0.LEON0.MCORE0.PROC0.IU0.IU1 .iu2.\ex_reg[RS1DATA][2] $hold( posedge CK:594, posedge D:594, limit: 1 ); I saw in...
See more

Part and Inventory Search

Back
Top