unbound componet vhdl error

[abu9022]

Hi Friends

Can you please help me how to solve the warning

Warning-[ELW_UNBOUND] Unbound component
  The component instantiation '/TBLEON/TB/P0/LEON0/MCORE0' (file:
  /mnt/iscsi/Users/ee5113/zxv764/leon2-1.0.30-xst/leon/leon_te.vhd, line: 141)
  will have no effect because component 'MCORE' is unbound. No entity
  definition for component 'MCORE' can be found in the following libraries (
  WORK  ) referenced by the architecture 'RTL' of entity 'LEON'.
  Please bind the component explicitly to an entity (architecture) pair, and
  verify that the pair was analyzed successfully.

leon_te.vhd

----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Lesser General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
--
--  See the file COPYING.LGPL for the full details of the license.


-----------------------------------------------------------------------------
-- Entity: 	leon
-- File:	leon.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Complete processor
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_map.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on

entity leon is
  port (
    resetn   : in    std_logic; 			-- system signals
    clk      : in    std_logic;
    te       : in    std_logic;
    pllref   : in    std_logic;
    plllock  : out   std_logic;

    errorn   : out   std_logic;
    address  : out   std_logic_vector(27 downto 0); 	-- memory bus

    data     : inout std_logic_vector(31 downto 0);

    ramsn    : out   std_logic_vector(4 downto 0);
    ramoen   : out   std_logic_vector(4 downto 0);
    rwen     : inout std_logic_vector(3 downto 0);
    romsn    : out   std_logic_vector(1 downto 0);
    iosn     : out   std_logic;
    oen      : out   std_logic;
    read     : out   std_logic;
    writen   : inout std_logic;

    brdyn    : in    std_logic;
    bexcn    : in    std_logic;

-- sdram i/f
    sdcke    : out std_logic_vector ( 1 downto 0);  -- clk en
    sdcsn    : out std_logic_vector ( 1 downto 0);  -- chip sel
    sdwen    : out std_logic;                       -- write en
    sdrasn   : out std_logic;                       -- row addr stb
    sdcasn   : out std_logic;                       -- col addr stb
    sddqm    : out std_logic_vector ( 7 downto 0);  -- data i/o mask
    sdclk    : out std_logic;                       -- sdram clk output
    sa       : out std_logic_vector(14 downto 0); 	-- optional sdram address
    sd       : inout std_logic_vector(63 downto 0); 	-- optional sdram data

    pio      : inout std_logic_vector(15 downto 0); 	-- I/O port

    wdogn    : out   std_logic;				-- watchdog output

    dsuen    : in    std_logic;
    dsutx    : out   std_logic;
    dsurx    : in    std_logic;
    dsubre   : in    std_logic;
    dsuact   : out   std_logic;
    test     : in    std_logic
  );
end;

architecture rtl of leon is

component mcore
  port (
    resetn   : in  std_logic;
    clk      : in  clk_type;
    te       : in  clk_type;
--    te       : in  std_logic;
    clkn     : in  clk_type;
    pciclk   : in  clk_type;
    memi     : in  memory_in_type;
    memo     : out memory_out_type;
    ioi      : in  io_in_type;
    ioo      : out io_out_type;
    pcii     : in  pci_in_type;
    pcio     : out pci_out_type;
    dsi      : in  dsuif_in_type;
    dso      : out dsuif_out_type;
    sdo      : out sdram_out_type;
    ethi     : in  eth_in_type;
    etho     : out eth_out_type;
    cgo      : in  clkgen_out_type;
    test     : in    std_logic
);
end component;

signal gnd, clko, sdclkl, resetno : std_logic;
signal clkm, clkn, pciclk : clk_type;
signal te_in    : std_logic;
signal memi     : memory_in_type;
signal memo     : memory_out_type;
signal ioi      : io_in_type;
signal ioo      : io_out_type;
signal pcii     : pci_in_type;
signal pcio     : pci_out_type;
signal dsi      : dsuif_in_type;
signal dso      : dsuif_out_type;
signal sdo      : sdram_out_type;
signal ethi     : eth_in_type;
signal etho     : eth_out_type;
signal cgi      : clkgen_in_type;
signal cgo      : clkgen_out_type;

--attribute keep_hierarchy : String;
--attribute keep_hierarchy of rtl : architecture is "yes";

begin
--  te <= te_in;
  gnd <= '0'; 
  cgi.pllctrl <= "00"; cgi.pllrst <= resetno; cgi.pllref <= pllref;

-- main processor core

  mcore0  : mcore
  port map (
    resetn => resetno, clk => clkm, te => te_in, clkn => clkn, pciclk => pciclk,
    memi => memi, memo => memo, ioi => ioi, ioo => ioo,
    pcii => pcii, pcio => pcio, dsi => dsi, dso => dso, sdo => sdo,
    ethi => ethi, etho => etho, cgo => cgo, test => test);

-- clock generator

  clkgen0 : clkgen  
  port map ( clko, clko, clkm, clkn, sdclkl, pciclk, cgi, cgo);

-- pads

--  clk_pad   : inpad port map (clk, clko);	-- clock
  clko <= clk;					-- avoid buffering during synthesis
  reset_pad   : smpad port map (resetn, resetno);	-- reset
  brdyn_pad   : inpad port map (brdyn, memi.brdyn);	-- bus ready
  bexcn_pad   : inpad port map (bexcn, memi.bexcn);	-- bus exception


    error_pad   : outpad generic map (2) port map (ioo.errorn, errorn);	-- cpu error mode

    d_pads: for i in 0 to 31 generate			-- data bus
      d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
    end generate;


    pio_pads : for i in 0 to 15 generate		-- parallel I/O port
      pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
    end generate;

    rwen_pads : for i in 0 to 3 generate			-- ram write strobe
      rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
    end generate;

     							-- I/O write strobe
    writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);

    a_pads: for i in 0 to 27 generate			-- memory address
      a_pad : outpad generic map (3) port map (memo.address(i), address(i));
    end generate;

    ramsn_pads : for i in 0 to 4 generate		-- ram oen/rasn
      ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
    end generate;

    ramoen_pads : for i in 0 to 4 generate		-- ram chip select
      ramoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
    end generate;

    romsn_pads : for i in 0 to 1 generate			-- rom chip select
      romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
    end generate;

    read_pad : outpad generic map (2) port map (memo.read, read);	-- memory read
    oen_pad  : outpad generic map (2) port map (memo.oen, oen);	-- memory oen
    iosn_pad : outpad generic map (2) port map (memo.iosn, iosn);	-- I/O select

    wd : if WDOGEN generate
      wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn);	-- watchdog output
    end generate;

    ds : if DEBUG_UNIT generate
      dsuen_pad   : inpad port map (dsuen, dsi.dsui.dsuen);	-- DSU enable
      dsutx_pad   : outpad generic map (1) port map (dso.dcomo.dsutx, dsutx);
      dsurx_pad   : inpad port map (dsurx, dsi.dcomi.dsurx);	-- DSU receive data
      dsubre_pad  : inpad port map (dsubre, dsi.dsui.dsubre);	-- DSU break
      dsuact_pad  : outpad generic map (1) port map (dso.dsuo.dsuact, dsuact);
    end generate;

    sdr : if SDRAMEN generate
      cs_pads: for i in 0 to 1 generate
        sdcke_pad  : outpad generic map (2) port map (sdo.sdcke(i), sdcke(i));
        sdcsn_pad  : outpad generic map (2) port map (sdo.sdcsn(i), sdcsn(i));
      end generate;
      sdwen_pad  : outpad generic map (2) port map (sdo.sdwen, sdwen);
      sdrasn_pad : outpad generic map (2) port map (sdo.rasn, sdrasn);
      sdcasn_pad : outpad generic map (2) port map (sdo.casn, sdcasn);
--      sdclk_pad : outpad generic map (2) port map (sdclkl, sdclk);
      sdclk <= sdclkl;  -- disable pad for simulation
      dqm_pads: for i in 0 to 3 generate
        sddqm_pad   : outpad generic map (2) port map (sdo.dqm(i), sddqm(i));
      end generate;
      sb : if SDSEPBUS generate
        sa_pads: for i in 0 to 14 generate			-- memory address
          p : outpad generic map (2) port map (memo.sa(i), sa(i));
        end generate;
        sd_pads: for i in 0 to 31 generate			-- data bus
          p : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.sd(i), sd(i));
        end generate;
        sb : if BUS64 generate
          dqm_pads: for i in 4 to 7 generate
            sddqm_pad   : outpad generic map (2) port map (sdo.dqm(i), sddqm(i));
          end generate;
          sd_pads: for i in 32 to 63 generate			-- data bus
            p : iopad generic map (3) port map (memo.data(i-32), memo.bdrive((63-i)/8), memi.sd(i), sd(i));
          end generate;
        end generate;
      end generate;
    end generate;

    pl : if TARGET_CLK /= gen generate
      plllock_pad : outpad generic map (2) port map (cgo.clklock, plllock);
    end generate;

end ;

 

[sharath666]

It basically means that you have not added the entity MCORE (having instance name MCORE0) to the list of files to be compiled.

 

[abu9022]

Hi sharath,

I added the file

mcore_te.vhd

----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Lesser General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
--
--  See the file COPYING.LGPL for the full details of the license.


-----------------------------------------------------------------------------
-- Entity: 	mcore
-- File:	mcore.vhd
-- Author:	Jiri Gaisler - Gaisler Reserch
-- Description:	Module containing the processor, caches, memory controller
--	        and standard peripherals
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
use work.ambacomp.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on

entity mcore is
  port (
    resetn   : in  std_logic;
    clk      : in  clk_type;
    te       : in  std_logic;
    clkn     : in  clk_type;
    pciclk   : in  clk_type;
    memi     : in  memory_in_type;
    memo     : out memory_out_type;
    ioi      : in  io_in_type;
    ioo      : out io_out_type;
    pcii     : in  pci_in_type;
    pcio     : out pci_out_type;
    dsi      : in  dsuif_in_type;
    dso      : out dsuif_out_type;
    sdo      : out sdram_out_type;
    ethi     : in eth_in_type;
    etho     : out eth_out_type;
    cgo      : in  clkgen_out_type;
    test     : in    std_logic
  );
end; 

architecture rtl of mcore is

component rstgen
port (
    rstin     : in  std_logic;
    pcirstin  : in  std_logic;
    clk       : in  clk_type;
    pciclk    : in  clk_type;
    rstout    : out std_logic;
    pcirstout : out std_logic;
    cgo       : in  clkgen_out_type
);
end component;

component dsu_mem
  port (
    clk    : in  clk_type;
    dmi    : in  dsumem_in_type;
    dmo    : out dsumem_out_type
  );
end component; 

component proc
port (
    rst    : in  std_logic;
    clk    : in  clk_type;                      -- main clock
    te     : in  std_logic;
    clkn   : in  clk_type;                      -- inverted main clock
    apbi   : in  apb_slv_in_type;
    apbo   : out apb_slv_out_type;
    ahbi   : in  ahb_mst_in_type;
    ahbo   : out ahb_mst_out_type;
    ahbsi  : in  ahb_slv_in_type;
    iui    : in  iu_in_type;
    iuo    : out iu_out_type

  );
end component;


signal rst   : std_logic;
signal iui   : iu_in_type;
signal iuo   : iu_out_type;
signal ahbsto: ahbstat_out_type;
signal mctrlo: mctrl_out_type;
signal wpo   : wprot_out_type;
signal apbi  : apb_slv_in_vector(0 to APB_SLV_MAX-1);
signal apbo  : apb_slv_out_vector(0 to APB_SLV_MAX-1);
signal ahbmi : ahb_mst_in_vector(0 to AHB_MST_MAX-1);
signal ahbmo : ahb_mst_out_vector(0 to AHB_MST_MAX-1);
signal ahbsi : ahb_slv_in_vector(0 to AHB_SLV_MAX-1);
signal ahbso : ahb_slv_out_vector(0 to AHB_SLV_MAX);
signal dsuo  : dsu_out_type;
signal dcomo : dcom_out_type;
signal te    : std_logic;
signal irqi   : irq_in_type;
signal irqo   : irq_out_type;
signal irq2i  : irq2_in_type;
signal irq2o  : irq2_out_type;
signal timo   : timers_out_type;
signal pioo   : pio_out_type;
signal uart1i, uart2i  : uart_in_type;
signal uart1o, uart2o  : uart_out_type;
signal dmi    : dsumem_in_type;
signal dmo    : dsumem_out_type;
signal pciirq : std_logic;
signal ethirq : std_logic;
signal pcirst : std_logic;
signal pciahb2: ahb_mst_out_type;

begin

-- reset generator

  reset0 : rstgen port map (resetn, pcii.pci_rst_in_n, clk, 
	   pciclk, rst, pcirst, cgo);


----------------------------------------------------------------------
-- AHB bus                                                          --
----------------------------------------------------------------------

-- AHB arbiter/decoder

  ahb0 : ahbarb 
	 generic map (masters => AHB_MASTERS, defmast => AHB_DEFMST)
	 port map (rst, clk, ahbmi(0 to AHB_MASTERS-1), 
	      ahbmo(0 to AHB_MASTERS-1), ahbsi, ahbso);

-- AHB/APB bridge

  apb0 : apbmst
	 port map (rst, clk, ahbsi(1), ahbso(1), apbi, apbo);

-- processor and cache sub-system

  proc0 : proc port map (
	rst, clk, te, clkn, apbi(2), apbo(2), ahbmi(0), ahbmo(0), 
	ahbsi(0), iui, iuo);

-- debug support unit
  dsugen : if DEBUG_UNIT generate
    dsu0 : dsu port map ( rst, clk, ahbmi(0), ahbsi(2), ahbso(2),
	              dsi.dsui, dsuo, iuo.debug, iui.debug, irqo, dmi, dmo);
    dso.dsuo <= dsuo;
    dsum0 : dsu_mem port map ( clk, dmi, dmo);
  end generate;
  dcomgen : if DEBUG_UNIT generate
    dcom0 : dcom 
            port map ( rst, clk, dsi.dcomi, dcomo, dsuo, apbi(11),
	    apbo(11), ahbmi(AHB_MASTERS-1), ahbmo(AHB_MASTERS-1) );
    dso.dcomo <= dcomo;
  end generate;

-- sram/prom/sdram memory controller

  mctrl0 : mctrl port map (
	rst => rst, clk=> clk, memi => memi, memo => memo,
	ahbsi => ahbsi(0), ahbso => ahbso(0), apbi => apbi(0), apbo => apbo(0), 
	pioo => pioo, wpo => wpo, sdo => sdo, mctrlo => mctrlo);

-- AHB ram
  aram0 : if AHBRAMEN generate
    aram : ahbram generic map (AHBRAM_BITS) 
           port map (rst, clk, ahbsi(4), ahbso(4));
  end generate;

-- AHB write protection

  wp0 : if WPROTEN generate
    wpm :  wprot port map ( 
	rst => rst, clk => clk, wpo => wpo,  ahbsi => ahbsi(0), 
	apbi => apbi(3), apbo => apbo(3));
  end generate;
  wp1 : if not WPROTEN generate apbo(3).prdata <= (others => '0'); end generate;

-- AHB status register

  as0 : if AHBSTATEN generate
    asm :  ahbstat port map ( 
	rst => rst, clk => clk, ahbmi => ahbmi(0), ahbsi => ahbsi(0), 
	apbi => apbi(1), apbo => apbo(1), ahbsto => ahbsto);
  end generate;

  as1 : if not AHBSTATEN generate 
    apbo(1).prdata <= (others => '0'); ahbsto.ahberr <= '0';
  end generate;

-- Optional PCI core

  pci0 : if PCIEN generate
    pci0 : pci
      port map ( resetn => rst, clk => clk, pciclk => pciclk,
        pcirst => pcirst, pcii => pcii, pcio => pcio,
        ahbmi1 => ahbmi(1), ahbmo1 => ahbmo(1),
        ahbsi => ahbsi(3), ahbso => ahbso(3),
        apbi => apbi(12), apbo => apbo(12), irq => pciirq);
  end generate;

  nopci : if not PCIEN generate pciirq <= '0'; end generate;

  eth0 : if ETHEN generate
    eth0 : eth_oc
    port map ( rst => rst, clk => clk,
               ahbsi => ahbsi(5), ahbso => ahbso(5),
               ahbmi  => ahbmi(PCIMASTERS+1), ahbmo => ahbmo(PCIMASTERS+1),
               eneti => ethi, eneto  => etho,
               irq => ethirq);
  end generate;
  noeth : if not ETHEN generate ethirq <= '0'; end generate;

-- drive unused part of the AHB bus to stop some stupid synthesis tools
-- from inserting tri-state buffers (!)  DISABLED

--  ahbdrv : for i in 0 to AHB_SLV_MAX-1 generate
--    u0 : if not AHB_SLVTABLE(i).enable and (AHB_SLVTABLE(i).index /= 0) generate
--      ahbso(AHB_SLVTABLE(i).index).hready <= '0'; 
--      ahbso(AHB_SLVTABLE(i).index).hresp  <= "--";
--      ahbso(AHB_SLVTABLE(i).index).hrdata <= (others => '-'); 
--      ahbso(AHB_SLVTABLE(i).index).hsplit <= (others => '-');
--    end generate;
--  end generate;

----------------------------------------------------------------------
-- APB bus                                                          --
----------------------------------------------------------------------

  pci_arb0 : if PCIARBEN generate
    pciarb : pci_arb
       port map (
         clk => pciclk, rst_n => pcirst,
         req_n => ioi.pci_arb_req_n, frame_n => pcii.pci_frame_in_n,
         gnt_n => ioo.pci_arb_gnt_n, pclk => clk, 
         prst_n => rst, pbi => apbi(13), pbo => apbo(13)
       );
  end generate;

-- LEON configuration register

  lc0 : if CFGREG generate
    lcm : lconf port map (rst => rst, apbo => apbo(4));
  end generate;

-- timers (and watchdog)

  timers0 : timers 
  port map (rst => rst, clk => clk, apbi => apbi(5), 
	    apbo => apbo(5), timo => timo, dsuo => dsuo);

-- UARTS
-- This stupidity exists because synopsys DC is not capable of
-- handling record elements in port maps. Sad really ...

  uart1i.rxd     <= pioo.rxd(0); uart1i.ctsn    <= pioo.ctsn(0);
  uart2i.rxd     <= pioo.rxd(1); uart2i.ctsn    <= pioo.ctsn(1);
  uart1i.scaler  <= pioo.io8lsb; uart2i.scaler  <= pioo.io8lsb;

  uart1 : uart port map ( 
    rst => rst, clk => clk, apbi => apbi(6), apbo => apbo(6), 
    uarti => uart1i, uarto => uart1o);
      
  uart2 : uart port map ( 
    rst => rst, clk => clk, apbi => apbi(7), apbo => apbo(7), 
    uarti => uart2i, uarto => uart2o);
      
-- interrupt controller

  irqctrl0 : irqctrl 
  port map (rst  => rst, clk  => clk, apbi => apbi(8), 
	    apbo => apbo(8), irqi => irqi, irqo => irqo);
  irqi.intack <= iuo.intack; irqi.irl <= iuo.irqvec; iui.irl <= irqo.irl;    

-- optional secondary interrupt controller

  i2 : if IRQ2EN generate
    irqctrl1 : irqctrl2
    port map (rst  => rst, clk  => clk, apbi => apbi(10), 
 	      apbo => apbo(10), irqi => irq2i, irqo => irq2o);
  end generate;

-- parallel I/O port

  ioport0 : ioport 
  port map (rst => rst, clk  => clk, apbi => apbi(9), apbo => apbo(9),
            uart1o => uart1o, uart2o => uart2o, mctrlo => mctrlo,
	    ioi => ioi, pioo => pioo);

-- drive unused part of the APB bus to stop some stupid synthesis tools
-- from inserting tri-state buffers (!) DISABLED

--  apbdrv : for i in 0 to APB_SLV_MAX-1 generate
--    u0 : if not APB_TABLE(i).enable and (APB_TABLE(i).index /= 0) generate
--	apbo( APB_TABLE(i).index).prdata <= (others => '-');
--    end generate;
--  end generate;

-- IRQ assignments, add you mapping below

  irqi.irq(15) <= '0';             -- unmaskable irq
  irqi.irq(14) <= pciirq;
  irqi.irq(13) <= '0';
  irqi.irq(12) <= ethirq;
  irqi.irq(11) <= dsuo.ntrace when DEBUG_UNIT else '0';
  irqi.irq(10) <= irq2o.irq when IRQ2EN else '0';
  irqi.irq(9) <=  timo.irq(1);		     -- timer 2
  irqi.irq(8) <=  timo.irq(0);		     -- timer 1
  irqi.irq(7 downto 4) <= pioo.irq;	     -- I/O port interrupts
  irqi.irq(3) <= uart1o.irq;		     -- UART 1
  irqi.irq(2) <= uart2o.irq;		     -- UART 2
  irqi.irq(1) <= ahbsto.ahberr;		     -- AHB error

  -- additional 32 interrupts for secondary interrupt controller
  irq2i.irq <= (others => '0');

-- drive outputs

  ioo.piol      <= pioo.piol(15 downto 0);
  ioo.piodir    <= pioo.piodir(15 downto 0);
  ioo.wdog      <= timo.wdog;
  ioo.errorn    <= iuo.error;




-- disassambler

-- pragma translate_off
  trace0 : trace(iuo.debug, (test = '1'));
-- pragma translate_on


end ;

 

[ads-ee]

Hi sharath,

I added the file

mcore_te.vhd

So did that fix the problem or are you still seeing a problem?

If you are still seeing errors, what are the compilation messages when you compile mcore_te.vhd and what is the command line for compiling that file?

 

[abu9022]

So did that fix the problem or are you still seeing a problem?

If you are still seeing errors, what are the compilation messages when you compile mcore_te.vhd and what is the command line for compiling that file?

I am still seeing the problem
I am running the command ./razor_script

razor_script

rm -rf ./csrc
rm -rf ./simv*
rm -rf ./work_vcs
mkdir ./work_vcs
#vlogan NangateOpenCellLibrary_slow_conditional.v
#vlogan gscl45nm.v
vhdlan -w work leon/std_logic_signed.vhd
vhdlan -w work leon/std_logic_unsigned.vhd
vhdlan -w work leon/std_logic_arith.vhd
vhdlan -w work leon/amba.vhd
vhdlan -w work leon/bprom.vhd
vhdlan -w work leon/target.vhd
vhdlan -w work leon/device.vhd
vhdlan -w work leon/config.vhd
vhdlan -w work leon/mmuconfig.vhd
vhdlan -w work leon/sparcv8.vhd
vhdlan -w work leon/iface.vhd
vhdlan -w work leon/macro.vhd
vhdlan -w work leon/ambacomp.vhd
vhdlan -w work leon/dma.vhd
vhdlan -w work leon/ahbmst.vhd
vhdlan -w work leon/tech_generic.vhd
vhdlan -w work leon/tech_virtex2.vhd
vhdlan -w work leon/tech_proasic.vhd
vhdlan -w work leon/tech_axcel.vhd
vhdlan -w work leon/tech_virtex.vhd
vhdlan -w work leon/tech_umc18.vhd
vhdlan -w work leon/tech_fs90.vhd
vhdlan -w work leon/tech_atc18.vhd
vhdlan -w work leon/tech_atc25.vhd
vhdlan -w work leon/tech_tsmc25.vhd
vhdlan -w work leon/tech_atc35.vhd
vhdlan -w work leon/multlib.vhd
vhdlan -w work leon/tech_map.vhd
vhdlan -w work leon/dsu.vhd
vhdlan -w work leon/dsu_mem.vhd
vhdlan -w work leon/dcom_uart.vhd
vhdlan -w work leon/dcom.vhd
vhdlan -w work leon/debug.vhd
vhdlan -w work leon/div.vhd
vhdlan -w work leon/mul.vhd
vhdlan -w work leon/ahbtest.vhd
vhdlan -w work leon/pci_gr.vhd
vhdlan -w work leon/ahbarb.vhd
vhdlan -w work leon/ahbstat.vhd
vhdlan -w work leon/wprot.vhd
vhdlan -w work leon/lconf.vhd
vhdlan -w work leon/acache.vhd
vhdlan -w work leon/mmu_acache.vhd
vhdlan -w work leon/apbmst.vhd
vhdlan -w work leon/ahbram.vhd
vhdlan -w work leon/rstgen.vhd
vhdlan -w work leon/meiko.vhd
vhdlan -w work leon/fpu_lth.vhd
vhdlan -w work leon/fpulib.vhd
vhdlan -w work leon/fpu_core.vhd
vhdlan -w work leon/grfpc.vhd
vhdlan -w work leon/fp1eu.vhd
#vlogan leon/iu_verilog3.v -v NangateOpenCellLibrary_slow_conditional.v
vlogan leon/iu_correct.v -v NangateOpenCellLibrary_slow_conditional.v
vlogan -sverilog leon/iu_veri11.sv
vhdlan -w work leon/iu_te.vhd
vhdlan -w work leon/dcache.vhd
vhdlan -w work leon/mmu_dcache.vhd
vhdlan -w work leon/icache.vhd
vhdlan -w work leon/mmu_icache.vhd
vhdlan -w work leon/mmu_cache.vhd
vhdlan -w work leon/cachemem.vhd
vhdlan -w work leon/cache.vhd
vhdlan -w work leon/proc_te.vhd
vhdlan -w work leon/irqctrl.vhd
vhdlan -w work leon/irqctrl2.vhd
vhdlan -w work leon/ioport.vhd
vhdlan -w work leon/timers.vhd
vhdlan -w work leon/pci_arb.vhd
vlogan leon/ethermac.v
vhdlan -w work leon/eth_oc.vhd
vhdlan -w work leon/pci.vhd
vhdlan -w work leon/uart.vhd
vhdlan -w work leon/sdmctrl.vhd
vhdlan -w work leon/mctrl.vhd
vhdlan -w work leon/mcore_te.vhd
#vlogan leon/leon.v -v NangateOpenCellLibrary_slow_conditional.v
vhdlan -w work leon/leon_te.vhd
vhdlan -w work leon/leon_pci.vhd
vhdlan -w work leon/leon_eth.vhd
vhdlan -w work leon/leon_eth_pci.vhd
vhdlan -w work leon/mmulrue.vhd
vhdlan -w work leon/mmulru.vhd
vhdlan -w work leon/mmutlbcam.vhd
vhdlan -w work leon/mmutlb.vhd
vhdlan -w work leon/mmutw.vhd
vhdlan -w work leon/mmu.vhd
vhdlan -w work leon/mmuconfig.vhd
vhdlan -w work tbench/iram.vhd
vhdlan -w work tbench/bprom.vhd
vhdlan -w work tbench/mspram.vhd
vhdlan -w work tbench/testmod.vhd
vhdlan -w work tbench/leonlib.vhd
vhdlan -w work tbench/tbgen_te.vhd
vhdlan -w work tbench/tb_msp.vhd
vhdlan -w work tbench/tblib.vhd
vhdlan -w work tbench/tbdef.vhd
vhdlan -w work tbench/tbleon.vhd
vhdlan -w work tbench/mt48lc16m16a2.vhd
#vcs -debug +delay_mode_zero work.tb_func32
vcs -debug  work.tb_func32 -gui
./simv -R -l tesTiming.out
#vcs -debug -ntb_opts tb_timescale=1ns/10ps work.tb_func32
#vcs -debug -R -l Log.log work.tb_func32
#./simv -ucli < one.scr

 

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What are the compilation messages? Optimally there should be no warnings during compilation, otherwise you may have problems due to some previous warning.

Also why are you asking in the Programmable logic section as this looks to be targeted to an ASIC and is using VCS. Most of the forum members that frequent this part of the forum don't work with ASIC and VCS. I've worked on ASICs, but have never used VCS. I've used Modelsim and Incisive.