abu9022
Member level 3
Hi Friends
when I am trying the command "report_timing", I am not getting Slack, but I am getting path is unconstrained
can you tell me How to solve Path is unconstrained
Below is my script file
can you check I need to add anything
when I am trying the command "report_timing", I am not getting Slack, but I am getting path is unconstrained
can you tell me How to solve Path is unconstrained
Below is my script file
can you check I need to add anything
Code:
#################################################
# list of all HDL files in the design
set myFiles [list leon/std_logic_signed.vhd leon/std_logic_unsigned.vhd leon/std_logic_arith.vhd leon/amba.vhd leon/target.vhd leon/device.vhd leon/config.vhd leon/sparcv8.vhd leon/mmuconfig.vhd leon/iface.vhd leon/macro.vhd leon/bprom.vhd leon/multlib.vhd leon/tech_generic.vhd leon/tech_virtex.vhd leon/tech_virtex2.vhd leon/tech_atc18.vhd leon/tech_atc25.vhd leon/tech_atc35.vhd leon/tech_fs90.vhd leon/tech_tsmc25.vhd leon/tech_umc18.vhd leon/tech_proasic.vhd leon/tech_axcel.vhd leon/tech_map.vhd leon/mmu_icache.vhd leon/mmu_dcache.vhd leon/mmu_acache.vhd leon/mmutlbcam.vhd leon/mmulrue.vhd leon/mmulru.vhd leon/mmutlb.vhd leon/mmutw.vhd leon/mmu.vhd leon/mmu_cache.vhd leon/cachemem.vhd leon/icache.vhd leon/dcache.vhd leon/acache.vhd leon/cache.vhd leon/ambacomp.vhd leon/apbmst.vhd leon/ahbmst.vhd leon/ahbstat.vhd leon/ahbtest.vhd leon/ahbram.vhd leon/ahbarb.vhd leon/lconf.vhd leon/fpulib.vhd leon/fpu_lth.vhd leon/meiko.vhd leon/fpu_core.vhd leon/grfpc.vhd leon/fp1eu.vhd leon/ioport.vhd leon/irqctrl.vhd leon/irqctrl2.vhd leon/sdmctrl.vhd leon/mctrl.vhd leon/rstgen.vhd leon/timers.vhd leon/uart.vhd leon/mul.vhd leon/div.vhd leon/iu.vhd leon/dcom_uart.vhd leon/dcom.vhd leon/dsu_mem.vhd leon/dsu.vhd leon/proc.vhd leon/wprot.vhd leon/mcore.vhd leon/leon.vhd]
#set basename leon
set basename iu;
set fileFormat vhdl;
set myClk clk;
set virtual 1;
set my_period_ns 7.0;
#set my_clk_freq_MHz 166.7
#set clock_skew = 0.10
#set my_input_delay_ns 0.0
##set my_output_delay_ns 0.0
set my_flatten 1; ##one yes, zero no
# runtime options
set runname clk7.0_td;
############################################
#Timing and loading Information
#set myClkLatency_ns 0.0;
#set myInDelay_ns 0.0;
#set myOutDelay_ns 0.0;
#set myMaxFanout 1;
#set myOutputLoad 0.1;
##########################################
#Library path
set search_path "$search_path /home/ee5323/mwj894/Nangate"
set target_library "NangateOpenCellLibrary_slow_conditional_nldm.db";
set link_library "* NangateOpenCellLibrary_slow_conditional_nldm.db";
#hdlin_ff_always_sync_set_reset = true
#hdlin_translate_off_skip_text = true
# analyze and elaborate verilog source files
set alib_library_analysis_path $search_path
define_design_lib WORK -path ./work
set verilogout_show_unconnected_pins "true"
#set vhdlout_unconnected_pin_prefix
#set_ultra_optimization true
#set_ultra_optimization -force
analyze -format $fileFormat -lib WORK $myFiles
elaborate $basename -lib WORK -update
current_design $basename
link
uniquify
#set my_period [expr 1000 / $my_clk_freq_MHz]
#set find_clock [ find port [list $my_clock_pin] ]
#if { $find_clock != [list] } {
# set clk_name $my_clock_pin
# create_clock -period $my_period $clk_name
#} else {
# set clk_name vclk
# create_clock -period $my_period -name $clk_name
#}
#set_input_delay $my_input_delay_ns -clock $clk_name [remove_from_collection [all_inputs] $my_clock_pin]
#set_output_delay $my_output_delay_ns -clock $clk_name [all_outputs]
if { $my_flatten == 1} {
compile -ungroup_all -map_effort medium
} elseif { $my_flatten == 0} {
compile -map_effort medium
}
#####################################################
#### setup clock and all input/output constraints####
#####################################################
echo SETTING CONSTRAINTS
#####################################################
#now you can create clock for the design
if{$virtual == 0} {
create_clock -period $myPeriod_ns $myClk
} else {
create_clock -period $myPeriod_ns -name $myClk
}
#set_clock_latency $myClkLatency_ns $myClk
####################################################
#set delays on all input and output with respect to the clock (in ns)
#set the input and output delay relative to myClk
#if { $virtual == 0} {
#set_input_delay $myInDelay_ns -clock $myClk [all_inputs]
#} else {
#set_input_delay $myInDelay_ns -clock $myClk [remove_from_collection [all_inputs] $myClk]
#}
#set_output_delay $myOutDelay_ns -clock $myClk [all_outputs]
####################################################
#other constraints
####################################################
#set_drive -rise 1 "clk"
#set_drive -fall 1 "clk"
#0 optimize for area, 1 optimize for timing driven
#set_max_area 1
#check design
check_design
check_timing
#compile the design
compile_ultra
check_design
echo VIOLATIONS
report_constraint -all_violators
#write -f db -hier -output leon_synth_166.7mhz_db.db
####################################################
# generate verilog code for synthesized module
# sdc file, sdf files, design compiler project
# and write out reports
###################################################
echo OUTPUT FILES AND REPORTS
set filebase [format "%s%s" [format "%s%s" $basename "_"] $runname]
#structural synthesized file as verilog
set filename [format "%s%s%s" ./src/ $filebase ".v"]
redirect change_names {change_names -rules verilog -hierarchy -verbose}
write -format verilog -hierarchy -output $filename
#write -f verilog -output iu_verilog7ns.v
#write -f vhdl -output iu_vhdl7ns.vhd
#write out the sdf file for back-annotated verilog sim
set filename [format "%s%s%s" ./src/ $filebase ".sdf" ]
write_sdf -version 1.0 $filename
#write_sdc iu_verilog7ns.sdc
#write_sdf iu_verilog7ns.sdf
set true_delay_prove_true_backtrack_limit 1000000
set true_delay_prove_false_backtrack_limit 1000000
#set_atpg -merge high -verbose
#run_atpg -auto
report_timing -true
#timing reports
set filename [format "%s%s%s" ./reports/ $filebase ".time" ]
redirect $filename {report_timing }
#timing reports
set filename [format "%s%s%s" ./reports/ $filebase ".timing" ]
redirect $filename {report_timing -nets -path full -delay max -max_path 20 -nworst 10}
#report_area
set filename [format "%s%s%s" ./reports/ $filebase ".area" ]
redirect $filename {report_area}
#report_power
set filename [format "%s%s%s" ./reports/ $filebase ".pow" ]
redirect $filename {report_power -analysis_effort low}
#report_timing -nets -path full -delay max -nworst 5000 -max_paths 5000 > iu_verilog7ns.5000worst
#report_timing -nets -path full -delay max -greater_path 2.0 -max_paths 5000 > iu_verilog7ns.5000greater2ns
#exit
#~
