Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
need for academic projects
We assist in all kind of acedemic projects. That includes B.Tech., M.Tech. and Phd. So what are you waiting for just drop me a mail on abhisheksbox@gmail.com will ur requirment and contact information.
Biasing of OPAMP
please dont see the peak values of bais, just find out the potential difference required for op-amp operation. for more clear answer plz provide more details abt the circuit.
Best way to get linearity is the use of a very stable bais circuit and keep the baise point as close as possible to the saturation point of the device for MOS technology.
Re: general question
0.8µm CMOS design means the design follows the model file defined by a fab lab, which can work for 0.8µm feature size. Or u can say that 0.8µm feature size is the minimum dimention that can be drown by a fab lab.
RF simulation
Terminate ur circuit at 50ohms of input and output impedence and run the simulation at any normal analog tool, by this may be u'll not get the exact behaviour of the circuit but u'll get an idea tht ur design is workin correctly or not.
specify the mode of diod
In anycase if the diode in the circuit is not power diode then it is on, otherwise it depends upon the specifications of the diode.
inductor model
Modelling of an inductor can be done in various ways, wht type of model can be used is depends upon the design methodology and the end objective of the circuit design.
cmos basics vgs
Saturation condition for mosfets is the condiction when the number of minority charge carriers at the channel becomes equal to numbe of mejority charge carriers in deep substrate.
look for the .out file after the simulation run for DC analysis with input voltage sweep from VDD to VSS, there u'll find all the pointsof analysis and there u can choose ur op points.
Introduce some intentional delays in all the signals other then the signal showing glitchs, for more discriptive answer plz mention ur code flow and i/o parameters.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.