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Can you give me some examples for my code to going on?
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If I have a signal connected the output of a component with the input of register file, In one of state I want to disconnect this signal then what's the value that will assigned to this signal in this...
Ok, let me explain more, my design is implementation for the following equation:
for(i = 1; i < 5; i++)
T += ( ((Rv[i] - Ru[i]))^2 + ((Iv[i] - Iu[i]))^2 )
assume the following:
1. use 4 add-sub, 2 squarer, and eight 21-bit register file(parallel input/output) .
2. finished all...
After I finished my design compilation on Quartus, I get multiple result for fmax as shown below. I want to know, what does it means? and How can I calculate the fmax of the all design?.
How can I get the fmax for a IP block created from Quartus Megafunction(such as lpm_add_sub)? also if there is a way to verify operation instead of writing test bench.
Note: I created lpm_add_sub block and started compilation, but I found "No paths to report" at fmax summary, I don't know the...
I have a confused in this question, Can any one give me an equation(additions and multiplications) where the max. clock cycles needed (given by ALAP schedule) should exceed the min. number of clock cycles needed (given by ASAP schedule ) by no less than 3 cycles.
I want to know the different (meaning) between the following two parts and how can I find them in quartus through timing analysis
i. The maximum internal clock frequency (clock for registered operation).
ii. The maximum frequency of variation of the input data.
After I write my VHDL code in Quartus and compiled it, I want to verify the proper operation of my code and create .vwf simulation file. How can I simulate and create .vwf file from modelsim?...please help