verify functionality and calculate fmax for Altera IP

[abd_elhamid_]

How can I get the fmax for a IP block created from Quartus Megafunction(such as lpm_add_sub)? also if there is a way to verify operation instead of writing test bench.

Note: I created lpm_add_sub block and started compilation, but I found "No paths to report" at fmax summary, I don't know the problem .

Any help.
Thanks

 

[sharath666]

There will not be any timing paths in this design. It must be a purely combinatorial circuit.

 

[TrickyDicky]

To get the fmax, you need a pipe depth of at least 2, because fmax comes from register to register path.

For a single mega wizard block, you can usually assume it will work as advertised, especially the lpm blocks, because they have a very long history. If you want to verify it, you will need a test bench.