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Thanks for your reply.
Oh. I miss it. Yes. as you can say that, if I use gain 1024/1023 buffer, I can solve LSB issue. However, for simple non-inverting gain control, I have to use 1 + 1023 resistor cells.
Because I have very small area in my chip, if I use 1 + 1023 resistor cell for gain...
I tried to design R2R DAC structure at in my circuit.
In my thought R2R DAC is more area effective DAC than conventional R-String DAC.
However, R2R DAC has some disadvantages.
1. VCR Issue
- In CMOS process, poly-silicon resistor or diffusion resistor has voltage coefficient. that is...
Hello.
During Fabrication Fault Analysis, I found metal short or open issue.
this picture shows top metal lines short.
This picture shows metal line open
In my opinion, it looks fabrication issue. because metal line's width is 0.8um, and space is not minimum.
max current is 110uA...
Today, we use BSIM level 47 or 49 model for transistor model. However, for better fast transient simulation, there are some transistor model like finite point based model.
Finite point based model is fast transient transistor model. However this model is not supported in hspice simulator...
How to design for low ripple Amplifier?
Hello. I have a question about low switching ripple amplifier.
Opamp configuration is above. two opamp outputs 13V & 10V. They loaded output capacitor 1nF. Switch period is 4us.
In switching period, switching ripple happens on the opamp output...
When I Rail to Rail OPAMP designed, I found that some opamp output range is really rail to rail.
For example, BUF16820 & BUF16821 INL/DNL specification is like this.
In BUF16820, when VDD power is 18V, INL measure voltage is 17V. So voltage difference of rail(VDD) and amp's output is 1V...
From "Design of Analog CMOS Integrated Circuits" by Razavi, I have a question about circuit analysis.
How do I transform from Fig. 3.23 (b) to Fig 3.23 (c) for circuit analysis?
I don't understand how M1's dependent source is changed to 1/(gm+gmb) resistor, especially one node is tied to...
Thank you for your reply.
Unfortunately, there is still a mysterious phenomenon that isn't explained with latch-up .
When opamp near-pin short issue is happen, short current flows through NMOS/PMOS and then protection flag signal is rising high. If short current is greater than 200mA for...
Thanks for your reply.
As you said, I added 10nF capacitor on A1 output, but the result is same(chip damage happened).
Next I added 47nF capacitor on A1 output. At this time, the result is different, chip is more robust to damage than no capacitance condition.
I don't know why more capacitance...
Even a piece of wire can be classed as inductive because it has a property of inductance.
I checked this one but over voltage is not measured.
A1 is large PMOS/NMOS drain terminal. We set this output voltage as 0V.
AVDD=18V, IAVDD is AVDD current by measured current probe.
During about...
Thanks for your reply.
In my explain, I said "I designed MOSFET switch". Its operation looks like "switch", But It's not switch. It's BUFFER's output stage.
PMOS/NMOS MOSFET is so large(Blue) , It can drive large current.
Red Voltage source is Test Voltage. It may be 18V.
When too much...
In CMOS Process, I designed Large NMOS/PMOS switch Transistor.
To protect switches from large Ids current, I designed protection circuit and inserted it.
It is supposed to operate when Ids current > 300mA , PMOS gate pull on(VDD) and NMOS gate pull down(GND). So Ids current doesnt flow any...
I want to tell confidently that latch-up is not the cause for "Unknown" damaged chip. I want to know "Unknown" damaged chip is damaged by some cause, not latch-up.
But I have no evidence for some other people.
But I don't know How to distinguish each other latch-up sample & unknown damaged...
Hello
I have two chips. one has a latch-up problem and the others does not. but this chip is damaged-chip too(not latch-up damage. but cause is unknown)
I want to distinguish each other which one is latch-up damaged and the other is not. Is there is way to distinguish two damaged-chip?
thanks
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