Forum: Digital Design and Embedded Programming
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ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions
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Timing during Synthesis: Max...
14th December 2018, 18:44
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Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.
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All design tool (compiler, assembler, linker) related questions. Embedded programming questions: assembler, C, C++, EC++, Pascal, Basic.
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Embedded Linux kernel, driver and application programming and system hardware design. Real-Time Operating Systems and other embedded operating systems.
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All questions related to Image processing, Audio processing. DSP hardware related questions.
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DSL, GSM, CDMA, WCDMA, OFDM, WiMAX, Communication Algorithm, SDR, DSProcessor, encoders, decoders
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PC programming language questions (Assembler, C, C++, Java, Pascal, Basic). Driver programming, algorithms.
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All types of network (telecomm. networks, data networks, internet...)
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Internet of Things (IoT) - M2M, Industrial IoT, and Industry 4.0. Hardware, systems, and software for the interconnection of embedded devices, wireless sensors networks, control systems, automation, and more.
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