Writing big sized test-cases in VHDL

[garvind25]

Hi,



I was writing test benches of VHDL codes (in VHDL) and came across a problem. I hope someone can help me.

While writing test benches for small number of inputs (say two or three one-bit inputs) I am able to cover all the case (four or eight cases). But when I have big sized inputs (or a large number of them), I am having difficulty. For eg. for testing a 8 bit adder which adds two 8-bit numbers, I will have to manually enter 2^8 * 2^8 input combinations (and off course the correct answer accompanying each test input pair).

Is there any other way to do so? Is there any way to automatically generate the 2^16 inputs? Also how to go about mentioning the corresponding outputs in the test bench?



Looking forward to your responses.



Thanks in advance,

Arvind Gupta.

 

[barry]

You could generate the inputs and expected results, and put them in text files and use TEXTIO functions to read them. Or, you could use GENERATE statements to create the values.

 

[TrickyDicky]

A for loop in a process is more likely a better option than a generate.

 

[barry]

A for loop in a process is more likely a better option than a generate.

Yeah, or that.