Wireload not generated?

[deathwaltz]

Hi，I am a freshman in ASIC.
Now I am playing with ETS pre-layout STA in setup stage.

I am assuming that WLM model is working because the variable is set by this sentence.
set_var enable_wire_load_model_support 1

but actually, the net delay is 0.000 and this is displayed behind
Wireload model(.lib None Generated)

Because I don't fully understand all ASIC design flow, I am not sure where the problem is.

I assume that the WLM is not set in lib at the synthesis stage. Isn't it right?
Or I did sth wrong?

Thank you very much.:grin:

 

[chipmonkey]

Normally we specify the wire load model during synthesis

 

[ljxpjpjljx]

yes, tools will provide us the wire load model!