VCS in EDA playground, not detecting module defined in another file

[analog_malware]

Hi,

My top module instantiates a module defined in another file with some parameters. The files are SystemVerilog, and the code synthesizes and simulates as expected in Vivado.

In EDA Playground, for some reason, I am getting an error every time the top module tries to instantiate the lower level module.

Error:
"
Error-[URMI] Unresolved modules
design.sv, 27
"indexed_rsh_mod #(.data_width_param(32), .idx_width_param(4), .sel_width_param(2)) idx_rsh_unit_0 ( .curr_arr_val (arr_sig[0]), .ins_val (insert_value), .arr_prev_val ('0), .idx (idx), .const_ref ('0), .new_arr_val (new_arr_sig[0]));"
Module definition of above instance is not found in the design.
"

 

[FvM]

I don't use the tool, but I remember we had previous posts about not recognized modules in EDA playground. If I remember right, the problem was that all modules must be loaded and defined in a project. Please consult web help.

 

[dpaul]

Hi,

My top module instantiates a module defined in another file with some parameters. The files are SystemVerilog, and the code synthesizes and simulates as expected in Vivado.

In EDA Playground, for some reason, I am getting an error every time the top module tries to instantiate the lower level module.

Error:
"
Error-[URMI] Unresolved modules
design.sv, 27
"indexed_rsh_mod #(.data_width_param(32), .idx_width_param(4), .sel_width_param(2)) idx_rsh_unit_0 ( .curr_arr_val (arr_sig[0]), .ins_val (insert_value), .arr_prev_val ('0), .idx (idx), .const_ref ('0), .new_arr_val (new_arr_sig[0]));"
Module definition of above instance is not found in the design.
"

1. Why do you worry and want to try out another simulator when the design is verified using Vivado simulator?
2. Since you say that the simulator is VCS, there might be special switches necessary to correctly compile your SV codes. Read some basic VCS documentation to find out (I do not use VCS and also do not use EDA Playground, so cannot give you a direct solution).