why jump up metal can solve the antenna effect?

[egg]

why jump up metal can solve the antenna effect?

anyone who can tell me the principle?

Thanks!

 

[abcyin]

Hi,

the key point is that the antenna effect occurs during the fabrication, during the construction, if no diode is connected to the poly gate, then collected charges will damage the gate oxide.

so, if the gate immediately connects to the highest level by jump-up metals, large amount of charges can not be collected, while the poly finally connected to the diffusion part by highest level, thus no antenna violation will normally occure.

hope it helps.

 

[deepak242003]

charge accumulation is directly proportional to ratio of fiel poly( and metal directly connected to it ) to active poly.. cumulative antenna..

when we do metal hoppping we actually decrease this ratio by reducing the metals directly connected to field poly.. thus decreasing the charge accumulation ...

 

[egg]

Hi,

the key point is that the antenna effect occurs during the fabrication, during the construction, if no diode is connected to the poly gate, then collected charges will damage the gate oxide.

so, if the gate immediately connects to the highest level by jump-up metals, large amount of charges can not be collected, while the poly finally connected to the diffusion part by highest level, thus no antenna violation will normally occure.

hope it helps.

Thanks for your reply.

But I still not understand, in the fabrication, when the below metal and up metal are both created, then the metal area is the same with before jump, and the gate
area is not change, so it would have antenna effect again, how did this happen?

Added after 17 minutes:

did I understand right?
I mean in block layout, when a net has antenna effect, for example, metal1, then I jump part of metal1 to metal2, then in the block drc, would be
ok, but in fact, if I did not jump it and when in the chip layout, this net has 2 choice, one is connected to S/D, the other is connected to Pad, this 2 choice would both has no antenna violation?
so, in my view, jump metal to fix antenna violation is not really fix, it was "delay" the violation and fix it by the progress, is this right?

Added after 4 minutes:

ps:

or the summary is:
in block level layout, antenna check is not necessary?

 

[erikl]

... or the summary is:
in block level layout, antenna check is not necessary?

Why not run the ARC anyway? It could find a missing (or broken) connection before extraction & LVS, thus could save time.

 

[dick_freebird]

Antenna charging goes with etch periphery, present layer.
Layers that have not yet been put down, contribute no charging.
Antenna discharge goes with gate tunneling current (gate area)
in the absence of antenna discharge diodes.


At the block level you may not have the conductor periphery
to fail, but it still might be better to standardize on an embedded
jumper, or put pins at a higher level in the stack, so you do not
have to go back later. You can design cells that are antenna-
clean by construction at the lower layers at least.

 

[abcyin]

Hi,

the key point is that the antenna effect occurs during the fabrication, during the construction, if no diode is connected to the poly gate, then collected charges will damage the gate oxide.

so, if the gate immediately connects to the highest level by jump-up metals, large amount of charges can not be collected, while the poly finally connected to the diffusion part by highest level, thus no antenna violation will normally occure.

hope it helps.

Thanks for your reply.

But I still not understand, in the fabrication, when the below metal and up metal are both created, then the metal area is the same with before jump, and the gate
area is not change, so it would have antenna effect again, how did this happen?

Added after 17 minutes:

did I understand right?
I mean in block layout, when a net has antenna effect, for example, metal1, then I jump part of metal1 to metal2, then in the block drc, would be
ok, but in fact, if I did not jump it and when in the chip layout, this net has 2 choice, one is connected to S/D, the other is connected to Pad, this 2 choice would both has no antenna violation?
so, in my view, jump metal to fix antenna violation is not really fix, it was "delay" the violation and fix it by the progress, is this right?

Added after 4 minutes:

ps:

or the summary is:
in block level layout, antenna check is not necessary?

Hi,
I try to explain it as simple as possible, if I could.
In the schematic, the gate is always connected to some drain/source diodes, for example, a cascaded inverter, the gate of 2nd inverter is connected to the drain/source diodes of the 1st inverter, that's to say, after fabrication, the charge could be discharged from the diodes, so that's why the charge will not damage the gate after fabrication.
However, during the fabiration, assume that you have only two metal levels, M1 and M2, if M1 is fabricated with big size, there is no discharge path for the accumlated charge, the gate oxide may be damaged.
so if the gate immediately connectes to the highest level, M2,(same size for M1), the gate is for sure already connected to the diode, so no antenna violation will normally occur.

And, I think you can get what you want from the following link:
https://en.wikipedia.org/wiki/Antenna_effect

Best wishes

 

[egg]

... or the summary is:
in block level layout, antenna check is not necessary?

Why not run the ARC anyway? It could find a missing (or broken) connection before extraction & LVS, thus could save time.

our drc check include arc check.

for jump, I mean m1 jump to m2, then jump to m1 again ,so there is no lvs error.

Added after 1 minutes:

Antenna charging goes with etch periphery, present layer.
Layers that have not yet been put down, contribute no charging.
Antenna discharge goes with gate tunneling current (gate area)
in the absence of antenna discharge diodes.


At the block level you may not have the conductor periphery
to fail, but it still might be better to standardize on an embedded
jumper, or put pins at a higher level in the stack, so you do not
have to go back later. You can design cells that are antenna-
clean by construction at the lower layers at least.

in layout view, you are right

Added after 25 minutes:

Hi,

the key point is that the antenna effect occurs during the fabrication, during the construction, if no diode is connected to the poly gate, then collected charges will damage the gate oxide.

so, if the gate immediately connects to the highest level by jump-up metals, large amount of charges can not be collected, while the poly finally connected to the diffusion part by highest level, thus no antenna violation will normally occure.

hope it helps.

Thanks for your reply.

But I still not understand, in the fabrication, when the below metal and up metal are both created, then the metal area is the same with before jump, and the gate
area is not change, so it would have antenna effect again, how did this happen?

Added after 17 minutes:

did I understand right?
I mean in block layout, when a net has antenna effect, for example, metal1, then I jump part of metal1 to metal2, then in the block drc, would be
ok, but in fact, if I did not jump it and when in the chip layout, this net has 2 choice, one is connected to S/D, the other is connected to Pad, this 2 choice would both has no antenna violation?
so, in my view, jump metal to fix antenna violation is not really fix, it was "delay" the violation and fix it by the progress, is this right?

Added after 4 minutes:

ps:

or the summary is:
in block level layout, antenna check is not necessary?

Hi,
I try to explain it as simple as possible, if I could.
In the schematic, the gate is always connected to some drain/source diodes, for example, a cascaded inverter, the gate of 2nd inverter is connected to the drain/source diodes of the 1st inverter, that's to say, after fabrication, the charge could be discharged from the diodes, so that's why the charge will not damage the gate after fabrication.
However, during the fabiration, assume that you have only two metal levels, M1 and M2, if M1 is fabricated with big size, there is no discharge path for the accumlated charge, the gate oxide may be damaged.
so if the gate immediately connectes to the highest level, M2,(same size for M1), the gate is for sure already connected to the diode, so no antenna violation will normally occur.

And, I think you can get what you want from the following link:
https://en.wikipedia.org/wiki/Antenna_effect

Best wishes

Hi Thanks for your explain.
For the red words, why jump to M2 then the gate is already connected to the diode?
in some times, we did not jump to the top metal but up metal(if metal layer more then 3), this can fix antenna violation too.

please see the below figure, if the m1 has antenna violation, I jump it to m2, then jump back to m1 again, this can fix the violation, but in the fabiration, when the m2 was made(via2, m3 was not made), the size of metal was big again, and this would call the m1 antenna violation again(I think), because the gate is the same, but the matal size is bigger, I am wonder where is the electron go?

Hope I said it clearly.
Thanks!

 

[kapilsn]

the charge accumulated during fabrication of a particular metal level are flushed before fabricating the next metal level.Hence there is nolarge change acculmulation .

Kapil

 

[egg]

the charge accumulated during fabrication of a particular metal level are flushed before fabricating the next metal level.Hence there is nolarge change acculmulation .

Kapil

did the process called anneal?

 

[shashikumar.22]

accumulated charges are removed in the Process called CMP chemical mechanical polishing/Planerization.

 

[kapilsn]

I also thought it was annealing
"annealing step heals the damage and causes the implanted dopant atoms to move into substitutional lattice sites."

should give a thought about CMP as it is a step between metal layers.

Isnt it that CMP was not in use for earlier technologies?
Kapil

 

[deepak242003]

I also thought it was annealing
"annealing step heals the damage and causes the implanted dopant atoms to move into substitutional lattice sites."

Annealing is done after implantation or diffusion eg well implantation as healing mechanisms..

should give a thought about CMP as it is a step between metal layers.

Right... it is used especially for copper metal layers fabrication . For details google ""dual-Damascene" process.

Isnt it that CMP was not in use for earlier technologies?
Kapil

yes.
above points answers it..

 

[erikl]

Guys, try to think physically:

The (positive) charge caught from the ion etch process is caught only by the current top metal (being etched), i.e. in case of m2 being etched, just by the m2 parts marked by "equal" signs ("=", thanks egg, I'm reusing your drawing!) :

Pad  ---
via3  o
m3   ---
via2  o
m2   ================                                =======
via1                o                                o     o
m1                  ----------------------------------     -----
cont                                                           O
gate                                                           ------

The caught charge is re-distributed on the total connected metal + poly area, of course, but the charge/area (and hence the generated voltage) is m2_area/total_connected_area. The ARC checks for the permitted value by calculating the area ratio.

The charge isn't flushed (removed) by an annealing or CMP process, but when the wafers are moved from the ion etch chamber to the wet cleaning (rinsing) station. Annealing happens much earlier, namely after the implant processes, (long) before metal layer deposition and etching. And CMP is done later, after deposition of the oxide/nitride (or whatever) insulation layer to the next metal layer.

Hope I could make this a bit clearer.

 

[egg]

Guys, try to think physically:

The (positive) charge caught from the ion etch process is caught only by the current top metal (being etched), i.e. in case of m2 being etched, just by the m2 parts marked by "equal" signs ("=", thanks egg, I'm reusing your drawing!) :

Pad  ---
via3  o
m3   ---
via2  o
m2   ================                                =======
via1                o                                o     o
m1                  ----------------------------------     -----
cont                                                           O
gate                                                           ------

The caught charge is re-distributed on the total connected metal + poly area, of course, but the charge/area (and hence the generated voltage) is m2_area/total_connected_area. The ARC checks for the permitted value by calculating the area ratio.

The charge isn't flushed (removed) by an annealing or CMP process, but when the wafers are moved from the ion etch chamber to the wet cleaning (rinsing) station. Annealing happens much earlier, namely after the implant processes, (long) before metal layer deposition and etching. And CMP is done later, after deposition of the oxide/nitride (or whatever) insulation layer to the next metal layer.

Hope I could make this a bit clearer.

Hi erikl,
Did you mean the charge was flushed in the "wet cleaning" step?

 

[deepak242003]

Pad  ---
via3  o
m3   ---
via2  o
m2   ================                                =======
via1                o                                o     o
m1                  ----------------------------------     -----
cont                                                           O
gate                                                           ------

The caught charge is re-distributed on the total connected metal + poly area, of course, but the charge/area (and hence the generated voltage) is m2_area/total_connected_area.

Is it the same as ratios recommended by foundry ..... ?/???
with few reference https://www.mosis.com/Technical/Designrules/guidelines.html]like this [/url]! and foundry manuals,
charge accumulated is proportional to
ratio of exposed metal ( here metal 2 ) to acitve gate area ..... OR
total area connected to gate to active gate area ( cumulative antenna ) ....
somewhat confused.....:?: :?: :?:

The charge isn't flushed (removed) by an annealing or CMP process, but when the wafers are moved from the ion etch chamber to the wet cleaning (rinsing) station.

.

Is it done at the end of fabrication all metal layers ??

:?:

 

[erikl]

Hi erikl,
Did you mean the charge was flushed in the "wet cleaning" step?

Sure: this creates the first overall short circuit on the wafer, after its removal from the ion etch chamber.
Actually I think the charge disappears immediately after the end of the ion beam etching, due to leakage.

Added after 10 minutes:

... ratio of exposed metal ( here metal 2 ) to acitve gate area ..... OR
total area connected to gate to active gate area ( cumulative antenna ) ....
somewhat confused.....:?: :?: :?:

The latter of course. Or would you think positive charges don't like metal1 and succeed in avoiding to stay there? ;-)

The charge isn't flushed (removed) by an annealing or CMP process, but when the wafers are moved from the ion etch chamber to the wet cleaning (rinsing) station.

Is it done at the end of fabrication all metal layers ??

No, after each etching step (actually after every process step).

 

[egg]

Thanks all!