kunal1514
Full Member level 1
Hi All,
Can anybody tell me that why "Initial" statement in verilog is not
synthesizable.
I want a qualifing and satisfactory answer.
Regard's
Kunal Mishra
Can anybody tell me that why "Initial" statement in verilog is not
synthesizable.
I want a qualifing and satisfactory answer.
Regard's
Kunal Mishra