Why "Initial" statement in Verilog is not synthesizable?

[kunal1514]

Hi All,

Can anybody tell me that why "Initial" statement in verilog is not
synthesizable.

I want a qualifing and satisfactory answer.

Regard's

Kunal Mishra

 

[hoangthanhtung]

Synthesis

I hope you can find question from this site

https://www.asic-world.com/verilog/synthesis2.html

 

[echo47]

Synthesis

If the target device provides automatic register initialization (FPGA/CPLD usually yes, ASIC usually no), then an initial statement should be synthesizable, unless the software authors neglected to implement it.

Xilinx XST (an FPGA/CPLD synthesizer) supports initial statements for registers and register arrays (RAM/ROM).
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[anantha_09]

Re: Synthesis

bcoz initial statements are incomplete without delays and u cannot have hardware logic or nets supporting delays.

if am wrong correct me