stackprogramer
Full Member level 3
The Std_logic_1164 package is the IEEE standard for describing digital logic values in VHDL (IEEE STD 1164). It contains definitions for std_logic (single bit) and for std_logic_vector (array).
In Verilog, there is a tool like std_logic_1164 in VHDL?
Thanks in advacne
In Verilog, there is a tool like std_logic_1164 in VHDL?
Thanks in advacne