[SOLVED] What's the alternative std logic VHDL in Verilog? (Std_logic_1164 package)

[stackprogramer]

The Std_logic_1164 package is the IEEE standard for describing digital logic values in VHDL (IEEE STD 1164). It contains definitions for std_logic (single bit) and for std_logic_vector (array).
In Verilog, there is a tool like std_logic_1164 in VHDL?

Thanks in advacne

 

[dpaul]

@stackprogramer,
In Verilog, there is a tool like std_logic_1164 in VHDL?

std_logic_1164 - that is a VHDL standard library, not a tool!
I think Verilog works in a differnet way.

 

[stackprogramer]

But the question for me remains, what is the equivalent of std logic in Verilog?

 

[TrickyDicky]

in verilog, the standard 4 state types are close enough. Any reg type will be a 4 state type
Z X 0 1

Verilog does not have a 9 state type to match the capabilities of VHDL's std_logic_1164