what's error in this vhdl code？

[lzh08]

--fdiv_even.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;

package fdiv_even IS
function div_even(ClkIn : in std_logic)
return std_logic;
end;

package body fdiv_even IS
SIGNAL Clk:std_logic;
function div_even(ClkIn : in std_logic)
return std_logic is
BEGIN
PROCESS(ClkIn)
BEGIN
IF ClkIn'event AND ClkIn='1' THEN
Clk<=NOT Clk;
END IF;
END PROCESS;
ClkOut<=Clk;

END;

--fdiv_even.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use work.fdiv_even.all;

entity div_top is
port
(
ClkIn : in std_logic;
ClkOut : out std_logic
);
end;

architecture action of div_top is

process(ClkIn)
begin
ClkOut <= div_even(ClkIn);
end process;
end;

 

[tkbits]

Is this for synthesis or simulation?

I would not be surprised if a synthesis tool refused to synthesize this code.

 

[Kukaz]

package body fdiv_even IS
SIGNAL Clk:std_logic; -- SIGNAL declaration can't be here
function div_even(ClkIn : in std_logic)
return std_logic is

-- VARIABLE declaration HERE
-- and RETURN variable, for example, ClkOut !

BEGIN

PROCESS(ClkIn) -- ONLY Sequential Statements... :-((
BEGIN
IF ClkIn'event AND ClkIn='1' THEN
Clk<=NOT Clk;
END IF;
END PROCESS;

ClkOut<=Clk;
-- Return function result HERE
-- for example, return ClkOut
END;