What circuits or methdology is used for frequency multiplier

[Anil Rana]

frequency multiplier fpga

hi all
What circuits or methdology is used for frequency multiplier?we know about the frequency divider which uses methods like counters to devide the frequecy.how freqency multilpier implemented in chips such as FPGAs?

 

[IanP]

Re: frequency multiplier

The best method of multiplying frequency is based on PLL.
Here you have a link to "PLL's in Cyclone II" FPGA:
https://www.altera.com/products/devices/cyclone2/features/cy2-pll_features.html
https://www.altera.com/support/devices/pll_clock/basics/pll-basics.html
Regards,
IanP

 

[kaiser]

Re: frequency multiplier

--Serial Multiplier Module--

module mult(clk, load, ain, bin, eb, done);

input clk, load; // clock and load/start signal
input [31:0] ain, bin;
// multiplier and multiplicand of n bits
output [63:0] eb; // product of 2n bits
output done; // product-ready signal

reg [31:0] a; // hold copy of multiplicand
reg [63:0] eb; // hold multiplier and product
reg done; // multiplication done and result ready signal
reg [5:0] i; // multiplication loop counter

initial begin done = 0; i = 0; end
// startup with done false and loop counter zero
// to allow correct function of 'always' block below

wire [32:0] s = eb[63:32] + ((eb[0]) ? a : 32'd0);
// 's' always holds the sum of the accum product
// and the low order of the multiplier times the
// multiplicand

always @(posedge clk) begin // it's a clocked system
if (load && (i==0)) begin // start a mult on load, if idle, (i==0)
done <= 0; // not done yet
a <= ain; // load the multiplicand
eb[63:32] <= 0; // zero the accumulated product
eb[31:0] <= bin; // load the multiplier
i <= 32; // set the loop counter
end
if (i!=0) begin // if multiplicant in progress
eb[63:0] <= {s, eb[31:1]};
// combined update of accum
// prod and shift of multiplier
i <= i-1; // decr loop count
if (i==1) done <= 1;// are we done yet?
end
end

endmodule

 

[dBUGGER]

frequency multiplier

hi,
PLL or a DCM(Digital Clock manager) is used to achieve the frequency multiplication/division or a clock phase shift.

Best regards,

 

[eeeraghu]

Re: frequency multiplier

The digital clock manager automatically manages the frequency multiplication and division according to the required input and outpu provided some constrains

 

[Anil Rana]

Re: frequency multiplier

thanks alot for helping me out.Will anybody of you clear what is DCM

 

[silencer3]

Re: frequency multiplier

DCM is Digital Clock Manager. This is a separate tool in XILINX ISE. using this we can generate an CORE which we can instantiate into our FPAG design and use it for any Frequecny manipulation such as multiplication or division.

 

[eeeraghu]

Re: frequency multiplier

Instead of configuring a clock pin to connect directly into an internal clock tree, that pin can be used to drive a special hard-wired function, called a clockmanager that generates a number of daughter clocks. these daughter clocks may be used to drive internal clock tree or external o/p pins that can be used to provide clocking services to other devices on the host circuit board.

each family of FPGA's have their own type of clock manager.

regards
raghu

 

[nhoctop]

Re: frequency multiplier

Thanks for your helping. But Could somebody give me one example to implement in FPGA and waveform of clock multiplying ? I need it very much. Thanks for your kind!