what is the component called for Converting 20-bit data @300Mhz to 30-bit data @200Mhz?

[neblung2018]

First of all, is it possible to convert 20-bit data @300Mhz to 30-bit data @200Mhz? (Assuming the clocks are async, so it could have any kind of phase different)

If it is possible, what is that component be called?

I came across things like "gearbox", "circular queue". But I cannot find more details on those things.

Also, I think a regular async FIFO is not going to achieve this because FIFO has same data width of its input/output

Thanks for any reply in advance!

 

[std_match]

You haven't specified the data alignment, but a simple solution could be to use a 60-bit wide async FIFO.
Combine three 20-bit words to a 60-bit word on the write side, and write with 100 MHz.
Read with 100 MHz and split the data to two 30-bit words.

 

[KlausST]

Hi,

It´s possible, but not that simple.

let´s say you have
* port A be 20 bit x 300 MHz as input
* and port B be 30 bit x 200 MHz as output

so it needs 3 cycles of port A to send 60 bits (3 x 20 bits = 60 bits)
and it needs 2 cycles of port B to receive 60 bits (2 x 30 bits = 60 bits)
Let´s call a packet of 30 bits a "frame".

Now you need to tell how the 60 bits of port A, (let´s name them A00U ... A19U, A00V ... A19V, A00W ... A19W, where U, V, W are the 3 input cycles)
are mapped to port B (let´s name them B00X ... B29X, B00Y ... B29Y, where X, Y are the two output cycles)

And you additionaly need to define how
* one can differ between cycles U, V, W in one frame
* one can differ between cycles X and Y in one frame

If you can´t give a uinque definition, then a safe data transfer is impossible, because you surely will mix from one frame to the other .. without knowing it.

****
Other problem:
How are those 200MHz and 300MHz clocks synchronized?
Are they divided down from one single clock?
Like 1.2GHz / 6 = 200MHz
and 1.2GHz / 4 = 300MHz
(This is the lowest jitter method I can think of)

If other method: explain and give timing / jitter informations.

****
Solution can be just some DFFs, some FIFOs, a PLD, ASIC...

Klaus

 

[D.A.(Tony)Stewart]

If the information rate is measured by 20 bit word rate 300/20 = 15 MHz, are you tossing 1/3 of your input data and replacing that space with some other source of data?

 

[barry]

If the information rate is measured by 20 bit word rate 300/20 = 15 MHz, are you tossing 1/3 of your input data and replacing that space with some other source of data?

Huh? The input data rate is 6000 M-bits/sec. The output data rate is 6000 M-bits/sec.

I think std-match is on the right track.

 

[D.A.(Tony)Stewart]

Huh? The input data rate is 6000 M-bits/sec. The output data rate is 6000 M-bits/sec.

I think std-match is on the right track.

Got it. This is just a simple example of frame relay breaking frames into packets. But requires overhead. In telephony 64bps 8 bit channels are bundled into larger frames. at much higher speeds both synchronous and async.