Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

VHDL: Problem with to_stdlogicvector

Status
Not open for further replies.
R

reninroy

Junior Member level 1
Joined
Feb 26, 2008
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,389
i am using a PCI core, While simulating it in Modelsim v6.2 its showing some problems in the command to_stdlogicvector. Error message is "to_stdlogicvector is either bit vector or logicvector. plz help me to solve this problem.thanks in advance....
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top