VHDL code for this timing diagram.

[vipinlal]

I want the signals to change as shown in the following timing diagram.The inputs are "busy" and "clk" and output is "dataenable".
These signals are used for interfacing my module with another module.Can anyone give a VHDL code or hardware circuit for this.Just plain ideas are also welcome.

The test bench used for creating this wave form is given below:

DataEnable <= '1';
wait for clk_period*2 ns;
DataEnable <= '0';
wait until Busy = '0';

thanks in advance,
vipin

 

[permute]

clocked process:
busy_d <= busy;

combinatorial:
dataenable <= not busy or not busy_d;

this would give the above response. keep in mind that busy_d needs to have an init of '1' and, if reset, needs to be reset to '1'. otherwise dataenable will be high on the first cycle out of reset even if busy is high.

 

[vipinlal]

That worked very well.Thanks a lot permute.