InS0mN1aC
Newbie level 3
Hello everyone,
I am new to VHDL and I have to write behavioral vhdl code for a 4-bit register with parallel load, using a D-Flip Flop. Here is the D-FF code i have to use:
Can you help me how to use this, in order to implement the register?
Thank you!!
I am new to VHDL and I have to write behavioral vhdl code for a 4-bit register with parallel load, using a D-Flip Flop. Here is the D-FF code i have to use:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port (d : in std_logic;
preset : in std_logic;
clear : in std_logic;
clk : in std_logic;
q : out std_logic);
end dff;
architecture bhv_dff of dff is
begin
process(clk, clear, preset)
begin
if clear = '0' then
q <= '0';
elsif preset = '1' then
q <= '1';
elsif clk'event and clk='1' then
q <= d;
end if;
end process;
end bhv_dff;
Can you help me how to use this, in order to implement the register?
Thank you!!