VHDL Code Error.Please Help.Urgent.

[bandanjot]

The first few lines of my code are:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use STD.TEXTIO.all;
use work.all;
constant MEM_SIZE: integer:= 4095; -- memory size


The error I am getting on my compilation:

gsm.vhd(6): near "constant": expecting: ARCHITECTURE CONFIGURATION ENTITY LIBRARY PACKAGE USE

I have checked numerous times , and I guess problem is with the line in which I define my constants. Can there by a problem in defining my libraries?? Are these libraries (eg. IEEE ,STD,work) available ?.

 

[FvM]

and I guess problem is with the line in which I define my constants.

The error meassage says very clearly, that a constant defintion isn't allowed in this place. That's the whole story.

Depending on what you are trying to achieve here, the constant definition can be used either inside the architecture part of a design unit or in a package header. Alternatively a generic constant in an entity definition can be a solution.

Consult a VHDL textbook or design examples/templates usually available with VHDL tools.

 

[victoria_jitesh]

Define constant in package or package body and then call that package in your program

 

[karikalan_t79]

declare constant in architecture part or in the pacakage of the design