eengr
Member level 4
Hi there I am working on a VHDL code to generate pwm outputs.
For each PWM output the ON & OFF time would be programmed into FPGA's dedicated registers from a microcontroller interface
The period / frequency would also be programmed by the microcontroller so there is a register for time period. My VHDL code is:
It synthesizes fine with no errors
I have used the an output port 'COUNT_OUT' just to check the value of my internal counter during ISIM simulation (otherwise it is not needed)
I have the following code for my test bench
I am testing 4 pwm outputs here
The period register is loaded with '10' (decimal)
The ON time for pwm 0 = 4
The OFF time for pwm 0 = 7
The ON time for pwm 1 = 7
The OFF time for pwm 1 = 4
So above two waveforms should be inverse of each other and they should start /stop at the counter values assigned to them '4' & '7'
The ON time for pwm 2 = 0
The OFF time for pwm 2 = 9
The ON time for pwm 3 = 9
The OFF time for pwm 3 = 0
Again So above two waveforms should be inverse of each other and they should start /stop at the counter values assigned to them '0' & '9'
When I do the simulation , I get the following results:
As you can see that
The ON time for pwm 0 = 6 instead of 4
The OFF time for pwm 0 = 8 instead of 7
The ON time for pwm 1 = 2 instead of 7
The OFF time for pwm 1 = 6 instead of 4
Although the above two waveforms appear exactly inverse of each other
For 2nd pair:
The ON time for pwm 2 = 2 instead of 0
The OFF time for pwm 2 = 1 instead of 9
The ON time for pwm 3 = 0 instead of 9
The OFF time for pwm 3 = 2 instead of 0
And the above waveforms are not inverse of each other either as in the 1st pair's case
I don't know if I am doing something wrong in main code OR test bench. Any help please!
For each PWM output the ON & OFF time would be programmed into FPGA's dedicated registers from a microcontroller interface
The period / frequency would also be programmed by the microcontroller so there is a register for time period. My VHDL code is:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity main_src is Port ( ISA_ABUS_IN : in STD_LOGIC_VECTOR (7 downto 0); ISA_DBUS_INOUT : inout STD_LOGIC_VECTOR (7 downto 0); ISA_IOR : in STD_LOGIC; ISA_IOW : in STD_LOGIC; -- ISA_SMEMR: in STD_LOGIC; -- ISA_SMEMW: in STD_LOGIC; -- ISA_MEMW: in STD_LOGIC; -- ISA_MEMR: in STD_LOGIC; -- ISA_BALE: in STD_LOGIC; -- ISA_AEN: in STD_LOGIC; -- ISA_IO16 : out STD_LOGIC; -- ISA_DATA_EN : out STD_LOGIC; -- Enable line for Level Shifter IC on Data Bus -- ISA_DATA_DIR: out STD_LOGIC; -- Direction line for Level Shifter IC on Data Bus -- ISA_CLK: in STD_LOGIC; -- ISA_OSC is clock signal coming from ISA BUS PC104 side FPGA_OSC : in STD_LOGIC; PWM_OUT : out STD_LOGIC_VECTOR (5 downto 0); COUNT_OUT : out STD_LOGIC_VECTOR (15 downto 0); FPGA_DBUS_OUT1: out STD_LOGIC_VECTOR (7 downto 0); FPGA_DBUS_OUT2: out STD_LOGIC_VECTOR (7 downto 0); FPGA_DBUS_IN1: in STD_LOGIC_VECTOR (7 downto 0)); end main_src; architecture Behavioral of main_src is signal ISA_DBUS1 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal ISA_DBUS2 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal FPGA_DBUS11 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal FPGA_DBUS21 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); signal en1 : STD_LOGIC; signal pwm_sig : STD_LOGIC_VECTOR (5 downto 0) := (others => '0'); -- Buffer registers signal bup1: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bdwn1: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bup2: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bdwn2: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bup3: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bdwn3: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bup4: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bdwn4: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bup5: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bdwn5: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bup6: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal bdwn6: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal btperiod: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- buffer Time period register -- Actual registers signal up1: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal dwn1: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal up2: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal dwn2: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal up3: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal dwn3: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal up4: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal dwn4: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal up5: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal dwn5: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal up6: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal dwn6: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal tperiod: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Time period register signal sreg: STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); -- status register signal tcount: STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Counter register -- Register Addresses constant ADDRESSUL1: STD_LOGIC_VECTOR (7 downto 0) := X"51"; -- Address for UP1 LOWER 8bits constant ADDRESSUH1: STD_LOGIC_VECTOR (7 downto 0) := X"52"; -- Address for UP1 HIGHER 8 bits constant ADDRESSDL1: STD_LOGIC_VECTOR (7 downto 0) := X"53"; -- Address for DWN1 LOWER 8bits constant ADDRESSDH1: STD_LOGIC_VECTOR (7 downto 0) := X"54"; -- Address for DWN1 HIGHER 8 bits constant ADDRESSUL2: STD_LOGIC_VECTOR (7 downto 0) := X"55"; -- Address for UP2 LOWER 8bits constant ADDRESSUH2: STD_LOGIC_VECTOR (7 downto 0) := X"56"; -- Address for UP2 HIGHER 8 bits constant ADDRESSDL2: STD_LOGIC_VECTOR (7 downto 0) := X"57"; -- Address for DWN2 LOWER 8bits constant ADDRESSDH2: STD_LOGIC_VECTOR (7 downto 0) := X"58"; -- Address for DWN2 HIGHER 8 bits constant ADDRESSUL3: STD_LOGIC_VECTOR (7 downto 0) := X"59"; -- Address for UP3 LOWER 8bits constant ADDRESSUH3: STD_LOGIC_VECTOR (7 downto 0) := X"5A"; -- Address for UP3 HIGHER 8 bits constant ADDRESSDL3: STD_LOGIC_VECTOR (7 downto 0) := X"5B"; -- Address for DWN3 LOWER 8bits constant ADDRESSDH3: STD_LOGIC_VECTOR (7 downto 0) := X"5C"; -- Address for DWN3 HIGHER 8 bits constant ADDRESSUL4: STD_LOGIC_VECTOR (7 downto 0) := X"5D"; -- Address for UP4 LOWER 8bits constant ADDRESSUH4: STD_LOGIC_VECTOR (7 downto 0) := X"5E"; -- Address for UP4 HIGHER 8 bits constant ADDRESSDL4: STD_LOGIC_VECTOR (7 downto 0) := X"5F"; -- Address for DWN4 LOWER 8bits constant ADDRESSDH4: STD_LOGIC_VECTOR (7 downto 0) := X"60"; -- Address for DWN4 HIGHER 8 bits constant ADDRESSUL5: STD_LOGIC_VECTOR (7 downto 0) := X"61"; -- Address for UP5 LOWER 8bits constant ADDRESSUH5: STD_LOGIC_VECTOR (7 downto 0) := X"62"; -- Address for UP5 HIGHER 8 bits constant ADDRESSDL5: STD_LOGIC_VECTOR (7 downto 0) := X"63"; -- Address for DWN5 LOWER 8bits constant ADDRESSDH5: STD_LOGIC_VECTOR (7 downto 0) := X"64"; -- Address for DWN5 HIGHER 8 bits constant ADDRESSUL6: STD_LOGIC_VECTOR (7 downto 0) := X"65"; -- Address for UP6 LOWER 8bits constant ADDRESSUH6: STD_LOGIC_VECTOR (7 downto 0) := X"66"; -- Address for UP6 HIGHER 8 bits constant ADDRESSDL6: STD_LOGIC_VECTOR (7 downto 0) := X"67"; -- Address for DWN7 LOWER 8bits constant ADDRESSDH6: STD_LOGIC_VECTOR (7 downto 0) := X"68"; -- Address for DWN7 HIGHER 8 bits -- How are we going to ensure that both bytes have been loaded before updating -- the PWM ON/OFF timings as it is 8 bit bus constant ADDRESSFQL: STD_LOGIC_VECTOR (7 downto 0) := X"69"; -- Address for PERIOD/FREQ LOWER 8 bits constant ADDRESSFQH: STD_LOGIC_VECTOR (7 downto 0) := X"6A"; -- Address for PERIOD/FREQ HIGHER 8 bits -- ADRSSTATS1 -- bits x-x-x-x-x-SC-LP-LC -- LC: Load Counter (UP/DOWNS) when '1' Buffer ready -- LP: Load Period when '1' Buffer ready -- SC : Start Counter - tcount when '1' constant ADRSSTATS1: STD_LOGIC_VECTOR (7 downto 0) := X"6B"; -- Address for STATUS REGISTER-1 begin -- main_pwm0_unit: entity work.pwm (pwm_arch) -- port map (FPGA_OSC => FPGA_OSC, PWM_OUT => PWM_OUT); ISA_DBUS1 <= ISA_DBUS_INOUT; -- Used as an input ISA_DBUS_INOUT <= ISA_DBUS2 when en1 = '1' else "ZZZZZZZZ"; -- Used as an output FPGA_DBUS_OUT1 <= FPGA_DBUS11; -- When value is written to output FPGA_DBUS_OUT2 <= FPGA_DBUS21; -- When value is written to output PWM_OUT(0) <= pwm_sig(0); PWM_OUT(1) <= pwm_sig(1); PWM_OUT(2) <= pwm_sig(2); PWM_OUT(3) <= pwm_sig(3); PWM_OUT(4) <= pwm_sig(4); PWM_OUT(5) <= pwm_sig(5); COUNT_OUT <= tcount ; process (FPGA_OSC) begin if (rising_edge (FPGA_OSC)) then if (ISA_IOW = '0' and ISA_IOR = '1') then -- Write is enabled en1 <= '0'; -- ISA_IO16 <= '0'; -- It is NOT an 16 bit device -- ISA_DATA_DIR <= '0'; -- Set Direction of Data Bus Level TxRx as ISA to FPGA -- ISA_DATA_EN <= '0'; -- Enable the Data Bus Level TxRx if (ISA_ABUS_IN = ADDRESSUL1) then -- if address is ADDRESSUL1 bup1 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUH1) then -- if address is ADDRESSUH1 bup1 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDL1) then -- if address is ADDRESSDL1 bdwn1 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDH1) then -- if address is ADDRESSDH1 bdwn1 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUL2) then -- if address is ADDRESSUL2 bup2 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUH2) then -- if address is ADDRESSUH2 bup2 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDL2) then -- if address is ADDRESSDL2 bdwn2 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDH2) then -- if address is ADDRESSDH2 bdwn2 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUL3) then -- if address is ADDRESSUL3 bup3 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUH3) then -- if address is ADDRESSUH3 bup3 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDL3) then -- if address is ADDRESSDL3 bdwn3 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDH3) then -- if address is ADDRESSDH3 bdwn3 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUL4) then -- if address is ADDRESSUL4 bup4 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUH4) then -- if address is ADDRESSUH4 bup4 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDL4) then -- if address is ADDRESSDL4 bdwn4 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDH4) then -- if address is ADDRESSDH4 bdwn4 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUL5) then -- if address is ADDRESSUL5 bup5 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUH5) then -- if address is ADDRESSUH5 bup5 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDL5) then -- if address is ADDRESSDL5 bdwn5 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDH5) then -- if address is ADDRESSDH5 bdwn5 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUL6) then -- if address is ADDRESSUL6 bup6 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSUH6) then -- if address is ADDRESSUH6 bup6 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDL6) then -- if address is ADDRESSDL6 bdwn6 (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSDH6) then -- if address is ADDRESSDH6 bdwn6 (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSFQL) then -- if address is ADDRESSFQL btperiod (7 downto 0) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADDRESSFQH) then -- if address is ADDRESSFQH btperiod (15 downto 8) <= ISA_DBUS1; elsif (ISA_ABUS_IN = ADRSSTATS1) then -- if address is ADRSSTATS1 sreg <= ISA_DBUS1; end if; end if; if (ISA_IOW = '1' and ISA_IOR = '0') then -- Read is enabled if (ISA_ABUS_IN = ADRSSTATS1) then -- if address is ADRSSTATS1 need to change this code en1 <= '1'; -- ISA_IO16 <= '0'; -- It is NOT an 16 bit device -- ISA_DATA_DIR <= '1'; -- Set Direction of Data Bus Level TxRx as FPGA to ISA -- ISA_DATA_EN <= '0'; -- Enable the Data Bus Level TxRx ISA_DBUS2 <= sreg; elsif (ISA_ABUS_IN = ADDRESSFQL) then -- if address is ADDRESSFQL need to change this code en1 <= '1'; -- ISA_IO16 <= '0'; -- It is NOT an 16 bit device -- ISA_DATA_DIR <= '1'; -- Set Direction of Data Bus Level TxRx as FPGA to ISA -- ISA_DATA_EN <= '0'; -- Enable the Data Bus Level TxRx ISA_DBUS2 <= tperiod (7 downto 0); elsif (ISA_ABUS_IN = ADDRESSFQH) then -- if address is ADDRESSFQH need to change this code en1 <= '1'; -- ISA_IO16 <= '0'; -- It is NOT an 16 bit device -- ISA_DATA_DIR <= '1'; -- Set Direction of Data Bus Level TxRx as FPGA to ISA -- ISA_DATA_EN <= '0'; -- Enable the Data Bus Level TxRx ISA_DBUS2 <= tperiod (15 downto 8); else en1 <= '0'; -- ISA_DATA_DIR <= '1'; -- Set Direction of Data Bus Level TxRx as FPGA to ISA -- ISA_DATA_EN <= '1'; -- Enable the Data Bus Level TxRx end if; end if; if (ISA_IOW = '1' and ISA_IOR = '1') then -- ERROR when both Write & Read are enabled at same time -- ISA_DATA_EN <= '1'; en1 <= '0'; end if; if (ISA_IOW = '0' and ISA_IOR = '0') then -- ERROR when both Write & Read are enabled at same time -- ISA_DATA_EN <= '1'; en1 <= '0'; end if; -- end if; -- if (rising_edge (FPGA_OSC)) then if (sreg(0) = '1') then --LC = '1' up1 <= bup1; up2 <= bup2; up3 <= bup3; up4 <= bup4; up5 <= bup5; up6 <= bup6; dwn1 <= bdwn1; dwn2 <= bdwn2; dwn3 <= bdwn3; dwn4 <= bdwn4; dwn5 <= bdwn5; dwn6 <= bdwn6; sreg(0) <= '0'; -- Reset the LC bit for PIC else end if; if (sreg(1) = '1') then -- LP = '1' tperiod <= btperiod; sreg (1) <= '0'; -- Reset the LP bit for PIC else end if; if (sreg(2) = '1') then if (tcount = (tperiod - 1) ) then tcount <= (others =>'0'); -- reset counter when reaches tperiod value else tcount <= tcount + 1; -- increment counter with each tick of 50MHz clock end if; end if; -- ***************************** PWM0 output start if (up1 < dwn1) then if (tcount > up1 and tcount < dwn1) then pwm_sig(0) <= '1'; else pwm_sig(0) <= '0'; end if; elsif (up1 > dwn1) then if (tcount > dwn1 and tcount < up1) then pwm_sig(0) <= '0'; else pwm_sig(0) <= '1'; end if; else pwm_sig(0) <= '0'; end if; -- ***************************** PWM0 output finish -- ***************************** PWM1 output start if (up2 < dwn2) then if (tcount > up2 and tcount < dwn2) then pwm_sig(1) <= '1'; else pwm_sig(1) <= '0'; end if; elsif (up2 > dwn2) then if (tcount > dwn2 and tcount < up2) then pwm_sig(1) <= '0'; else pwm_sig(1) <= '1'; end if; else pwm_sig(1) <= '0'; end if; -- ***************************** PWM1 output finish -- ***************************** PWM2 output start if (up3 < dwn3) then if (tcount > up3 and tcount < dwn3) then pwm_sig(2) <= '1'; else pwm_sig(2) <= '0'; end if; elsif (up3 > dwn3) then if (tcount > dwn3 and tcount < up3) then pwm_sig(2) <= '0'; else pwm_sig(2) <= '1'; end if; else pwm_sig(2) <= '0'; end if; -- ***************************** PWM2 output finish -- ***************************** PWM3 output start if (up4 < dwn4) then if (tcount > up4 and tcount < dwn4) then pwm_sig(3) <= '1'; else pwm_sig(3) <= '0'; end if; elsif (up4 > dwn4) then if (tcount > dwn4 and tcount < up4) then pwm_sig(3) <= '0'; else pwm_sig(3) <= '1'; end if; else pwm_sig(3) <= '0'; end if; -- ***************************** PWM3 output finish -- ***************************** PWM4 output start if (up5 < dwn5) then if (tcount > up5 and tcount < dwn5) then pwm_sig(4) <= '1'; else pwm_sig(4) <= '0'; end if; elsif (up5 > dwn5) then if (tcount > dwn5 and tcount < up5) then pwm_sig(4) <= '0'; else pwm_sig(4) <= '1'; end if; else pwm_sig(4) <= '0'; end if; -- ***************************** PWM4 output finish -- ***************************** PWM5 output start if (up6 < dwn6) then if (tcount > up6 and tcount < dwn6) then pwm_sig(5) <= '1'; else pwm_sig(5) <= '0'; end if; elsif (up6 > dwn6) then if (tcount > dwn6 and tcount < up6) then pwm_sig(5) <= '0'; else pwm_sig(5) <= '1'; end if; else pwm_sig(5) <= '0'; end if; -- ***************************** PWM5 output finish end if; end process; end Behavioral;
It synthesizes fine with no errors
I have used the an output port 'COUNT_OUT' just to check the value of my internal counter during ISIM simulation (otherwise it is not needed)
I have the following code for my test bench
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY FCBR_main_TB8 IS END FCBR_main_TB8; ARCHITECTURE behavior OF FCBR_main_TB8 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT main_src PORT( ISA_ABUS_IN : IN std_logic_vector(7 downto 0); ISA_DBUS_INOUT : INOUT std_logic_vector(7 downto 0); ISA_IOR : IN std_logic; ISA_IOW : IN std_logic; FPGA_OSC : IN std_logic; PWM_OUT : OUT std_logic_vector(5 downto 0); COUNT_OUT : out STD_LOGIC_VECTOR (15 downto 0); FPGA_DBUS_OUT1 : OUT std_logic_vector(7 downto 0); FPGA_DBUS_OUT2 : OUT std_logic_vector(7 downto 0); FPGA_DBUS_IN1 : IN std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal ISA_ABUS_IN : std_logic_vector(7 downto 0) := (others => '0'); signal ISA_IOR : std_logic := '0'; signal ISA_IOW : std_logic := '0'; signal FPGA_OSC : std_logic := '0'; signal FPGA_DBUS_IN1 : std_logic_vector(7 downto 0) := (others => '0'); --BiDirs signal ISA_DBUS_INOUT : std_logic_vector(7 downto 0); --Outputs signal PWM_OUT : std_logic_vector(5 downto 0); signal COUNT_OUT : STD_LOGIC_VECTOR (15 downto 0); signal FPGA_DBUS_OUT1 : std_logic_vector(7 downto 0); signal FPGA_DBUS_OUT2 : std_logic_vector(7 downto 0); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name constant FPGA_OSC_period : time := 20 ns; -- 50MHz clock constant ADDRESSUL1: STD_LOGIC_VECTOR (7 downto 0) := X"51"; -- Address for UP1 LOWER 8bits constant ADDRESSUH1: STD_LOGIC_VECTOR (7 downto 0) := X"52"; -- Address for UP1 HIGHER 8 bits constant ADDRESSDL1: STD_LOGIC_VECTOR (7 downto 0) := X"53"; -- Address for DWN1 LOWER 8bits constant ADDRESSDH1: STD_LOGIC_VECTOR (7 downto 0) := X"54"; -- Address for DWN1 HIGHER 8 bits constant ADDRESSUL2: STD_LOGIC_VECTOR (7 downto 0) := X"55"; -- Address for UP2 LOWER 8bits constant ADDRESSUH2: STD_LOGIC_VECTOR (7 downto 0) := X"56"; -- Address for UP2 HIGHER 8 bits constant ADDRESSDL2: STD_LOGIC_VECTOR (7 downto 0) := X"57"; -- Address for DWN2 LOWER 8bits constant ADDRESSDH2: STD_LOGIC_VECTOR (7 downto 0) := X"58"; -- Address for DWN2 HIGHER 8 bits constant ADDRESSUL3: STD_LOGIC_VECTOR (7 downto 0) := X"59"; -- Address for UP3 LOWER 8bits constant ADDRESSUH3: STD_LOGIC_VECTOR (7 downto 0) := X"5A"; -- Address for UP3 HIGHER 8 bits constant ADDRESSDL3: STD_LOGIC_VECTOR (7 downto 0) := X"5B"; -- Address for DWN3 LOWER 8bits constant ADDRESSDH3: STD_LOGIC_VECTOR (7 downto 0) := X"5C"; -- Address for DWN3 HIGHER 8 bits constant ADDRESSUL4: STD_LOGIC_VECTOR (7 downto 0) := X"5D"; -- Address for UP4 LOWER 8bits constant ADDRESSUH4: STD_LOGIC_VECTOR (7 downto 0) := X"5E"; -- Address for UP4 HIGHER 8 bits constant ADDRESSDL4: STD_LOGIC_VECTOR (7 downto 0) := X"5F"; -- Address for DWN4 LOWER 8bits constant ADDRESSDH4: STD_LOGIC_VECTOR (7 downto 0) := X"60"; -- Address for DWN4 HIGHER 8 bits constant ADDRESSUL5: STD_LOGIC_VECTOR (7 downto 0) := X"61"; -- Address for UP5 LOWER 8bits constant ADDRESSUH5: STD_LOGIC_VECTOR (7 downto 0) := X"62"; -- Address for UP5 HIGHER 8 bits constant ADDRESSDL5: STD_LOGIC_VECTOR (7 downto 0) := X"63"; -- Address for DWN5 LOWER 8bits constant ADDRESSDH5: STD_LOGIC_VECTOR (7 downto 0) := X"64"; -- Address for DWN5 HIGHER 8 bits constant ADDRESSUL6: STD_LOGIC_VECTOR (7 downto 0) := X"65"; -- Address for UP6 LOWER 8bits constant ADDRESSUH6: STD_LOGIC_VECTOR (7 downto 0) := X"66"; -- Address for UP6 HIGHER 8 bits constant ADDRESSDL6: STD_LOGIC_VECTOR (7 downto 0) := X"67"; -- Address for DWN7 LOWER 8bits constant ADDRESSDH6: STD_LOGIC_VECTOR (7 downto 0) := X"68"; -- Address for DWN7 HIGHER 8 bits constant ADDRESSFQL: STD_LOGIC_VECTOR (7 downto 0) := X"69"; -- Address for PERIOD/FREQ LOWER 8 bits constant ADDRESSFQH: STD_LOGIC_VECTOR (7 downto 0) := X"6A"; -- Address for PERIOD/FREQ HIGHER 8 bits -- ADRSSTATS1 -- bits x-x-x-x-x-SC-LP-LC -- LC: Load Counter (UP/DOWNS) when '1' Buffer ready -- LP: Load Period when '1' Buffer ready constant ADRSSTATS1: STD_LOGIC_VECTOR (7 downto 0) := X"6B"; -- Address for STATUS REGISTER-1 constant PWM0ULB: STD_LOGIC_VECTOR (7 downto 0) := X"F4"; -- Start @ 500 = X01F4 constant PWM0UHB: STD_LOGIC_VECTOR (7 downto 0) := X"01"; -- Start @ 500 = X01F4 constant PWM0DLB: STD_LOGIC_VECTOR (7 downto 0) := X"E9"; -- Start @ 1001 = X03E9 constant PWM0DHB: STD_LOGIC_VECTOR (7 downto 0) := X"03"; -- Start @ 1001 = X03E9 constant PWM1ULB: STD_LOGIC_VECTOR (7 downto 0) := X"9B"; -- Start @ 667 = X029B constant PWM1UHB: STD_LOGIC_VECTOR (7 downto 0) := X"02"; -- Start @ 667 = X029B constant PWM1DLB: STD_LOGIC_VECTOR (7 downto 0) := X"A6"; -- Start @ 166 = X00A6 constant PWM1DHB: STD_LOGIC_VECTOR (7 downto 0) := X"00"; -- Start @ 166 = X00A6 constant PWM2ULB: STD_LOGIC_VECTOR (7 downto 0) := X"43"; -- Start @ 835 = X0343 constant PWM2UHB: STD_LOGIC_VECTOR (7 downto 0) := X"03"; -- Start @ 835 = X0343 constant PWM2DLB: STD_LOGIC_VECTOR (7 downto 0) := X"38"; -- Start @ 1336 = X0538 constant PWM2DHB: STD_LOGIC_VECTOR (7 downto 0) := X"05"; -- Start @ 1336 = X0538 constant PWM3ULB: STD_LOGIC_VECTOR (7 downto 0) := X"EA"; -- Start @ 1002 = X03EA constant PWM3UHB: STD_LOGIC_VECTOR (7 downto 0) := X"03"; -- Start @ 1002 = X03EA constant PWM3DLB: STD_LOGIC_VECTOR (7 downto 0) := X"DF"; -- Start @ 1503 = X05DF constant PWM3DHB: STD_LOGIC_VECTOR (7 downto 0) := X"05"; -- Start @ 1503 = X05DF constant PWM4ULB: STD_LOGIC_VECTOR (7 downto 0) := X"91"; -- Start @ 1169 = X0491 constant PWM4UHB: STD_LOGIC_VECTOR (7 downto 0) := X"04"; -- Start @ 1169 = X0491 constant PWM4DLB: STD_LOGIC_VECTOR (7 downto 0) := X"86"; -- Start @ 1670 = X0686 constant PWM4DHB: STD_LOGIC_VECTOR (7 downto 0) := X"06"; -- Start @ 1670 = X0686 constant PWM5ULB: STD_LOGIC_VECTOR (7 downto 0) := X"38"; -- Start @ 1336 = X0538 constant PWM5UHB: STD_LOGIC_VECTOR (7 downto 0) := X"05"; -- Start @ 1336 = X0538 constant PWM5DLB: STD_LOGIC_VECTOR (7 downto 0) := X"2D"; -- Start @ 1837 = X072D constant PWM5DHB: STD_LOGIC_VECTOR (7 downto 0) := X"07"; -- Start @ 1837 = X072D constant STATLC: STD_LOGIC_VECTOR (7 downto 0) := X"01"; -- Status register has LC bit set constant STATLP: STD_LOGIC_VECTOR (7 downto 0) := X"02"; -- Status register has LP bit set constant STATSC: STD_LOGIC_VECTOR (7 downto 0) := X"04"; -- Status register has SC bit set constant PERIODLB: STD_LOGIC_VECTOR (7 downto 0) := X"EA"; -- Start @ 1002 = X03EA constant PERIODHB: STD_LOGIC_VECTOR (7 downto 0) := X"03"; -- Start @ 1002 = X03EA BEGIN -- Instantiate the Unit Under Test (UUT) uut: main_src PORT MAP ( ISA_ABUS_IN => ISA_ABUS_IN, ISA_DBUS_INOUT => ISA_DBUS_INOUT, ISA_IOR => ISA_IOR, ISA_IOW => ISA_IOW, FPGA_OSC => FPGA_OSC, PWM_OUT => PWM_OUT, COUNT_OUT => COUNT_OUT, FPGA_DBUS_OUT1 => FPGA_DBUS_OUT1, FPGA_DBUS_OUT2 => FPGA_DBUS_OUT2, FPGA_DBUS_IN1 => FPGA_DBUS_IN1 ); -- Clock process definitions FPGA_OSC_process :process begin FPGA_OSC <= '0'; wait for FPGA_OSC_period/2; FPGA_OSC <= '1'; wait for FPGA_OSC_period/2; end process; -- Stimulus process stim_proc: process begin wait for FPGA_OSC_period*10; FPGA_DBUS_IN1 <= PWM0ULB; ISA_IOW <= '1'; ISA_IOR <= '0'; -- nothing should happen for above ISA_DBUS_INOUT<="ZZZZZZZZ"; wait for FPGA_OSC_period*2; --******************* Write is enabled now onwards ISA_IOW <= '0'; -- write cycle enabled ISA_IOR <= '1'; wait for FPGA_OSC_period*2; --******************* Load PERIOD LOW byte ISA_ABUS_IN <= ADDRESSFQL; ISA_DBUS_INOUT <= X"0A"; wait for FPGA_OSC_period*2; --******************* Load PERIOD HIGH byte ISA_ABUS_IN <= ADDRESSFQH; ISA_DBUS_INOUT <= X"00"; wait for FPGA_OSC_period*2; --******************* Load pwm0 UP LOW byte ISA_DBUS_INOUT <= X"04"; ISA_ABUS_IN <= ADDRESSUL1; wait for FPGA_OSC_period*2; --******************* Load pwm0 UP HIGH byte ISA_ABUS_IN <= ADDRESSUH1; ISA_DBUS_INOUT <= X"00"; wait for FPGA_OSC_period*2; --******************* Load pwm0 DOWN LOW byte ISA_DBUS_INOUT <= X"07"; ISA_ABUS_IN <= ADDRESSDL1; wait for FPGA_OSC_period*2; --******************* Load pwm0 DOWN HIGH byte ISA_ABUS_IN <= ADDRESSDH1; ISA_DBUS_INOUT <= X"00"; wait for FPGA_OSC_period*2; -- ********************************************************************* --******************* Load pwm1 UP LOW byte ISA_DBUS_INOUT <= X"07"; ISA_ABUS_IN <= ADDRESSUL2; wait for FPGA_OSC_period*2; --******************* Load pwm1 UP HIGH byte ISA_ABUS_IN <= ADDRESSUH2; ISA_DBUS_INOUT <= X"00"; wait for FPGA_OSC_period*2; --******************* Load pwm1 DOWN LOW byte ISA_DBUS_INOUT <= X"04"; ISA_ABUS_IN <= ADDRESSDL2; wait for FPGA_OSC_period*2; --******************* Load pwm1 DOWN HIGH byte ISA_ABUS_IN <= ADDRESSDH2; ISA_DBUS_INOUT <= X"00"; wait for FPGA_OSC_period*2; -- ********************************************************************* --******************* Load pwm2 UP LOW byte ISA_DBUS_INOUT <= X"00"; ISA_ABUS_IN <= ADDRESSUL3; wait for FPGA_OSC_period*2; --******************* Load pwm2 UP HIGH byte ISA_ABUS_IN <= ADDRESSUH3; ISA_DBUS_INOUT <= X"00"; wait for FPGA_OSC_period*2; --******************* Load pwm2 DOWN LOW byte ISA_DBUS_INOUT <= X"09"; ISA_ABUS_IN <= ADDRESSDL3; wait for FPGA_OSC_period*2; --******************* Load pwm2 DOWN HIGH byte ISA_ABUS_IN <= ADDRESSDH3; ISA_DBUS_INOUT <= X"09"; wait for FPGA_OSC_period*2; -- ********************************************************************* --******************* Load pwm3 UP LOW byte ISA_DBUS_INOUT <= X"09"; ISA_ABUS_IN <= ADDRESSUL4; wait for FPGA_OSC_period*2; --******************* Load pwm3 UP HIGH byte ISA_ABUS_IN <= ADDRESSUH4; ISA_DBUS_INOUT <= X"00"; wait for FPGA_OSC_period*2; --******************* Load pwm3 DOWN LOW byte ISA_DBUS_INOUT <= X"00"; ISA_ABUS_IN <= ADDRESSDL4; wait for FPGA_OSC_period*2; --******************* Load pwm3 DOWN HIGH byte ISA_ABUS_IN <= ADDRESSDH4; ISA_DBUS_INOUT <= X"00"; wait for FPGA_OSC_period*2; -- ********************************************************************* --******************* Load STATUS REGISTER with all there members 'SET' LC, L, & SC ISA_ABUS_IN <= ADRSSTATS1; ISA_DBUS_INOUT <="00000111"; wait for FPGA_OSC_period*1; --******************* Set Address bus to an invalid Address ISA_ABUS_IN <= X"FF"; wait for FPGA_OSC_period*2; wait for FPGA_OSC_period*50; -- wait for FPGA_OSC_period*10000; assert false report "NS Simulation Completed" severity failure; -- hold reset state for 100 ns. end process; END;
I am testing 4 pwm outputs here
The period register is loaded with '10' (decimal)
The ON time for pwm 0 = 4
The OFF time for pwm 0 = 7
The ON time for pwm 1 = 7
The OFF time for pwm 1 = 4
So above two waveforms should be inverse of each other and they should start /stop at the counter values assigned to them '4' & '7'
The ON time for pwm 2 = 0
The OFF time for pwm 2 = 9
The ON time for pwm 3 = 9
The OFF time for pwm 3 = 0
Again So above two waveforms should be inverse of each other and they should start /stop at the counter values assigned to them '0' & '9'
When I do the simulation , I get the following results:
As you can see that
The ON time for pwm 0 = 6 instead of 4
The OFF time for pwm 0 = 8 instead of 7
The ON time for pwm 1 = 2 instead of 7
The OFF time for pwm 1 = 6 instead of 4
Although the above two waveforms appear exactly inverse of each other
For 2nd pair:
The ON time for pwm 2 = 2 instead of 0
The OFF time for pwm 2 = 1 instead of 9
The ON time for pwm 3 = 0 instead of 9
The OFF time for pwm 3 = 2 instead of 0
And the above waveforms are not inverse of each other either as in the 1st pair's case
I don't know if I am doing something wrong in main code OR test bench. Any help please!