addisualemayehu
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I am designing the 8255 peripheral interface function in to Spartan 3E familly. using VHDL code by XILINX software but now when i compile my code it says:
the full codes are below.
ERROR:HDLCompiler:806 - "C:/Users/Addi/Documents/project/vlsi_vhdl/ppi8255/ppi8255.vhd" Line 367: Syntax error near "process".
the full codes are below.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:29:15 02/15/2014 -- Design Name: -- Module Name: ppi8255 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ppi8255 is Port (D0 :inout STD_LOGIC; D1 :inout std_logic; D2 :inout std_logic; D3 :inout std_logic; D4 :inout std_logic; D5 :inout std_logic; D6 :inout std_logic; D7 :inout std_logic; PORTA : inout std_logic_vector (7 downto 0); PORTB : inout std_logic_vector (7 downto 0); C0 : inout std_logic; C1 : inout std_logic; C2 : inout std_logic; C3 : inout std_logic; C4 : inout std_logic; C5 : inout std_logic; C6 : inout std_logic; C7 : inout std_logic; A1A0 :in std_logic_vector (1 DOWNTO 0); WRITE : in STD_LOGIC; READ : in STD_LOGIC; RESET : in STD_LOGIC; CS : in STD_LOGIC); end ppi8255; architecture Behavioral of ppi8255 is signal ck:std_logic; signal d3d2d1:std_logic_vector(2 downto 0); signal d6d5:std_logic_vector(1 downto 0); signal d4d3:std_logic_vector(1 downto 0); begin process(PORTA,PORTB,D0,D1,D2,D3,D4,D5,D6,D7,A1A0,READ,WRITE,RESET,CS,C0,C1,C2,C3,C4,C5,C6,C7) begin (D3,D2,D1) <= to_stdulogicvector(D3D2D1); (D6,D5) <= to_stdulogicvector(d6d5); (D3,D2,D1) <= to_stdulogicvector(D3D2D1); IF cs='1' then ---TRI-STATE CONDITION THAT IT STAYS HOLDING THE INPUTS UPTO WHEN CS=0 D0<=D0; D1<=D1; D2<=D2; D3<=D3; D4<=D4; D5<=D5; D6<=D6; D7<=D7; PORTA<=PORTA; PORTB<= PORTB; C0<=C0; C1<=C1; C2<=C2; C3<=C3; C4<=C4; C5<=C5; C6<=C6; C7<=C7; ELSIF cs='0' THEN CASE A1A0 IS WHEN "00" => -- this means using the porta only as i/o IF READ ='0' AND WRITE ='1' THEN ----IF THE MICROPROCESSOR WANT TO READ THE READ PORT OF PPI WILL BE ACTIVE LOW(0) AND TEH WRITE PORT OF THE PPI WILL BE ACTIVE HIGH(1) (D0,D1,D2,D3,D4,D5,D6,D7)<=PORTA; ELSIF READ ='1' AND WRITE ='0' THEN ----IF THE MICROPROCESSOR WANT TO WRITE ON THE PPI THE WRITE PORT OF PPI WILL BE ACTIVE LOW(0) AND TEH READ PORT OF THE PPI WILL BE ACTIVE HIGH(1) PORTA<=(D0,D1,D2,D3,D4,D5,D6,D7); END IF; WHEN "01"=> --- this is for uning the portb only as i/o IF READ ='0' AND WRITE='1' THEN (D0,D1,D2,D3,D4,D5,D6,D7) <= PORTB; ELSIF READ ='1' AND WRITE ='0' THEN PORTB <= (D0,D1,D2,D3,D4,D5,D6,D7); END IF; WHEN "10"=> --- use for the portc us i/o IF READ ='0' AND WRITE='1' THEN D0<=C0; D1<=C1; D2<=C2; D3<=C3; D4<=C4; D5<=C5; D6<=C6; D7<=C7; ELSIF READ ='1' AND WRITE ='0' THEN C0<=D0; C1<=D1; C2<=D2; C3<=D3; C4<=D4; C5<=D5; C6<=D6; C7<=D7; END IF; WHEN "11"=> --comand register IF READ ='1' AND WRITE ='0' THEN--write is activated by making write active low becouse the comand byte b works only for write operation IF D7<='0' THEN ---comand byte b IF D0<='1' THEN --- seting command byte CASE D3D2D1 IS WHEN "000" => C0<=C0; WHEN "001" => C1<=C1; WHEN "010" => C2<=C2; WHEN "011" => C3<=C3; WHEN "100" => C4<=C4; WHEN "101" => C5<=C5; WHEN"110" => C6<=C6; WHEN "111" => C7<=C7; WHEN OTHERS=> END CASE; ELSIF D0<='0' THEN ----Reseting means changing the out put CASE d3d2d1 IS WHEN "000" => C0<=NOT(C0); WHEN "001" => C1<=NOT(C1); WHEN "010" => C2<=NOT(C2); WHEN "011" => C3<=NOT(C3); WHEN "100" => C4<=NOT(C4); WHEN "101" => C5<=NOT(C5); WHEN "110" => C6<=NOT(C6); WHEN "111" => C7<=NOT(C7); WHEN OTHERS=> END CASE; END IF; END IF; END IF; IF D7='1' THEN CASE D6D5 IS WHEN "00" => IF READ ='0' AND WRITE ='1' THEN --- the microprocessor is activating the read operation by making the the read port activ low that means the microprocssor is reding the input from the input divice therough the ppi sequentialy as ordered. IF (D4='1') THEN (D7,D6,D5,D4,D3,D2,D1,D0)<= PORTA; ELSIF (D3='1') THEN D4<=C4; D5<=C5; D6<=C6; D7<=C7; END IF; ELSIF READ ='1' AND WRITE ='0' THEN IF (d4='0') THEN PORTA <= (D7,D6,D5,D4,D3,D2,D1,D0); ELSIF (d3='0') THEN C4<=D4; C5<=D5; C6<=D6; C7<=D7; END IF; END IF; WHEN "01"=> ---- for mode 1 CASE D4 IS WHEN '1' => IF C4='0' THEN ----when stb is active low C5<='0'; ----input buffer full C3<='0'; ---- interrupt IF (C5='0' AND C4='0') THEN (D7,D6,D5,D4,D3,D2,D1,D0)<= PORTA; END IF; ELSIF C4='1' THEN C5<='1'; C3<='1'; IF READ<='0' THEN C3<= NOT(C3); END IF; IF (C5='1' AND C4='1') THEN PORTA <= PORTA; END IF; END IF; IF D3 ='1' THEN D6<=C6; D7<=C7; ELSIF D3 ='0' THEN C6<=D6; C7<=D7; END IF; WHEN OTHERS => IF D3 ='0' THEN C4 <= D4; C5 <=D5; ELSIF D3 ='1' THEN D4<=C4; D5<=C5; END IF; IF C6='0' THEN C7<='0'; C3<='0'; IF (C7='0' AND C3='0') THEN PORTA <= (D7,D6,D5,D4,D3,D2,D1,D0); END IF; ELSIF C6='1' THEN C7<='1'; C3 <='1'; IF (C7='1' AND C3='1') THEN D0<=D0; D1<=D1; D2<=D2; D3<=D3; D4<=D4; D5<=D5; D6<=D6; D7<=D7; END IF; END IF; END CASE; WHEN OTHERS => IF D4 = '1' THEN if D3 = '1' THEN D0 <= C0; D1 <= C1; D2 <= C2; ELSIF d3 = '0' THEN C0 <= D0; C1 <= D1; C2 <= D2; END IF; END IF; IF READ = '0' AND WRITE = '1' THEN IF D0 ='1' THEN D0<=C0; D1<=C1; D2<=C2; END IF; IF C4 = '1' THEN C5 <='1'; C3 <='1'; IF (C4 ='1' AND C3 ='1') THEN D0<=D0; D1<=D1; D2<=D2; D3<=D3; D4<=D4; D5<=D5; D6<=D6; D7<=D7; END IF; ELSIF C4 = '0' THEN C5 <= '0'; C3 <= '0'; IF (C4 ='0' AND C3 ='0') THEN PORTA <= (D7,D6,D5,D4,D3,D2,D1,D0); END IF; END IF; ELSIF READ = '1' AND WRITE = '0' THEN IF D0 ='0' THEN C0<=D0; C1<=D1; C2<=D2; END IF; IF C6 = '1' THEN C7<='1'; C3<='1'; IF (C6 = '1' AND C3 ='1') THEN PORTA<= PORTA; END IF; ELSIF C6 = '0' THEN C7<='0'; C3<='0'; IF (C6 = '0' AND C3 ='0') THEN (D7,D6,D5,D4,D3,D2,D1,D0)<= PORTA; END IF; END IF; END IF; END CASE; CASE D2 IS WHEN '1' => IF D1 ='1' THEN IF C2 ='0' THEN C1<= '0'; C0<= '0'; IF C0 <= '0' AND C2 <= '0' THEN (D7,D6,D5,D4,D3,D2,D1,D0)<= PORTB; END IF; ELSIF c2 = '1' THEN C1 <= '1'; C0 <= '1'; IF C0<='1' AND C2 <= '1' THEN PORTB <= PORTB; END IF; END IF; ELSIF D1='0' THEN IF C2 ='0' THEN C1<= '0'; C0<= '0'; IF C0 <= '0' AND C2 <= '0' THEN PORTB <=(D7,D6,D5,D4,D3,D2,D1,D0); END IF; ELSIF c2 = '1' THEN C1 <= '1'; C0 <= '1'; IF C0<='1' AND C2 <= '1' THEN D0<=D0; D1<=D1; D2<=D2; D3<=D3; D4<=D4; D5<=D5; D6<=D6; D7<=D7; END IF; END IF; END IF; WHEN OTHERS => END CASE; END IF; end process; end Behavioral;
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