very urgent.................

[midovambir]

we i simulate my vhdl program this error appear .
"Formal port in component <euclid> must be an identifier"
can any one help me to overcome this problem...........thanks

 

[monalishap]

which tool are you using?

 

[midovambir]

i use Xilinx ise 10.1

 

[monalishap]

r u using the tool in windows?
with which programme are u finding the error?
plz.. post the programme...