Verilog use $random, why random seed be force changed? How use $random with seed?

[luoyanghero]

//This is the verilog standard document discription:
//The seed argument controls the numbers that $random returns so that different seeds generate different random streams. The seed argument shall be an integral variable. The seed value should be assigned to this variable prior to calling $random.
//I did a test.

`ifndef DLY
`define DLY 1
`endif

module tb_top;
reg             clk_bus;
reg             brst_n;
reg [31:0] frame_cnt;
reg [31:0] cnt;

initial begin
    brst_n = 1'b1;
    #1;
    brst_n = 1'b0;
    #100;
    brst_n = 1'b1;
    #1000000000;
    //$finish;
end

initial begin
    clk_bus = 1'b0;
    forever #5 clk_bus = ~clk_bus;
end

always @ (posedge clk_bus or negedge brst_n) begin
    if (~brst_n)
        cnt[31:0] <= #`DLY 'd0;
    else
        cnt[31:0] <= #`DLY cnt + 1;
end
always @ (posedge clk_bus or negedge brst_n) begin
    if (~brst_n)
        frame_cnt[31:0] <= #`DLY 32'd0;
    else if (cnt==1000)
        frame_cnt[31:0] <= #`DLY frame_cnt + 1;
end

integer end_dly;
initial begin
    end_dly = 1;
    while (1) begin
        @(posedge clk_bus);
        if (cnt==1001) begin
            #`DLY end_dly = $random(frame_cnt[7:0]);//luoy why random seed(frame_cnt[7:0]) be force changed?
        end
    end
end

initial begin
        //wait ((in_data_drv.frm_cnt == 1) && (in_data_drv.mb_y_cnt == 90));
        $fsdbDumpfile("tb_top.fsdb");
        $fsdbDumpvars(tb_top, 0);
end
endmodule

//frame_cnt be force changed from 32'h1 to 32'hce.

 

[ThisIsNotSam]

I think you don't understand what a seed is.

 

[luoyanghero]

I think you don't understand what a seed is.

I think you don't understand what a seed is.

Emmm, is there an example how to use a seed?

 

[BradtheRad]

In BASIC a common practice is to do something like RND(timer) or RND(0-timer) at the beginning of the program.

It seems like an odd requirement but there's a common characteristic of random number commands, that the routine generates the same series of 'random values' if you start with the same seed value. Therefore you ought to start with a different seed value when you run the program.

 

[ThisIsNotSam]

Emmm, is there an example how to use a seed?

there are literally a hundred examples if you google "verilog random seed"

 

[luoyanghero]

there are literally a hundred examples if you google "verilog random seed"

Thanks a lot. The following site given the $random details.
http://www.testbench.in/TB_15_SYSTEM_FUNCTION_RANDOM_A_MYTH.html
Seed is an in-out, so I need seed variable.
##############
Random number system function has a argument called seed. The seed parameter controls the numbers that $random returns such that different seeds generate different random streams. The seed parameter shall be either a reg, an integer, or a time variable. The seed value should be assigned to this variable prior to calling $random. For each system function, the seed parameter is an in-out parameter; that is, a value is passed to the function
and a different value is returned.



EXAMPLE:
module Tb();
integer num,seed,i,j;

initial
begin
for(j = 0;j<4 ;j=j+1)
begin
seed = j;
$display(" seed is %d",seed);
for(i = 0;i < 10; i=i+1)
begin
num = { $random(seed) } % 10;
$write("| num=%2d |",num);
end
$display(" ");
end
end
endmodule

RESULT:

seed is 0
| num= 8 || num= 7 || num= 7 || num= 7 || num= 7 || num= 7 || num= 5 || num= 2 || num= 1 || num= 9 |
seed is 1
| num= 8 || num= 8 || num= 2 || num= 2 || num= 6 || num= 3 || num= 8 || num= 5 || num= 5 || num= 5 |
seed is 2
| num= 8 || num= 1 || num= 0 || num= 5 || num= 0 || num= 8 || num= 6 || num= 7 || num= 1 || num= 6 |
seed is 3
| num= 8 || num= 2 || num= 2 || num= 3 || num= 8 || num= 6 || num= 1 || num= 4 || num= 3 || num= 9 |
##################