vedic multiplier for 4*4 bits

[sushma67]

it is showing near port map can anyone check plssss

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Code VHDL - [expand]
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Code for 4*4  vedic multiplier 
Adder
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(a:in std_logic_vector(3 downto 0);sum:out std_logic;carry:out std_logic);
end adder;
architecture behavior of adder is
signal c0,s0:std_logic:=’0’;
begin
s0<=a0 xor a1 xor a2;
c0<=(a0 and a1) or (a1 and a2)or( a2 and a1);
sum<=a3 xor s0 xor c0;
carry<=(a3 and s0)or (s0 and c0) or (a3 and c0);
end behaviour;
vedic multiplier
library ieee;
use ieee.std_logic_1164.all;
entity vedic mul is
port(x,y:in std_logic_vector(3 downto 0);r: out std_logic_vector(6 downto 0);cout: out std_logic);
end vedic mul;
architecture behaviour of vedic mul is
signal c:std_logic_vector(15 downto 1);
signal d:std_logic_vector(4 downto 0);
component adder
port(a:in std_logic_vector(3 downto 0);sum:out std_logic;carry:out std_logic);
end component;
begin
r(0)<=x(0) and y(0);
c(1)<=x(0) and y(1);
c(2)<=x(1) and y(0);
c(3)<=x(0) and y(2);
c(4)<=x(1) and y(1);
c(5)<=x(2) and y(0);
c(6)<=x(0) and y(3);
c(7)<=x(1) and y(2);
c(8)<=x(2) and y(1);
c(9)<=x(3) and y(0);
c(10)<=x(1) and y(3);
c(11)<=x(2) and y(2);
c(12)<=x(3) and y(1);
c(13)<=x(2) and y(3);
c(14)<=x(3) and y(2);
c(15)<=x(3) and y(3);
adder port map(c(1),c(2),r(1),d(0));
adder port map(c(3),c(4),c(5),d(0),r(2),d(1));
adder port map(c(6),c(7),c(8),c(9),d(1),r(3),d(2));
adder port map(c(10),c(11),c(12),d(2),r(4),d(3));
adder port map(c(13),c(14),d(3),r(5),d(4));
adder port map(c(15),d(4),r(6),cout);
end behaviour;

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[TrickyDicky]

you need to give the adders idividiual labels:

eg:

adder1 : adder port map ();

 

[kalidasascreator]

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
entity adder is
port(a:in std_logic_vector(3 downto 0);
sum:out std_logic;carry:out std_logic);
end adder;
architecture behaviour of adder is
signal c0,s0:std_logic:='0';
begin
s0<=a(0) xor a(1) xor a(2);
c0<=(a(0) and a(1)) or (a(1) and a(2))or( a(2) and a(1));
sum<=a(3) xor s0 xor c0;
carry<=(a(3) and s0)or (s0 and c0) or (a(3) and c0);
end behaviour;
 
--vedic multiplier
library ieee;
use ieee.std_logic_1164.all;
 
entity vedic_mul is
port(x,y:in std_logic_vector(3 downto 0);r: out std_logic_vector(6 downto 0);
cout: out std_logic);
end vedic_mul;
 
architecture behaviour of vedic_mul is
signal c:std_logic_vector(15 downto 1);
signal d:std_logic_vector(4 downto 0);
component adder
port(a:in std_logic_vector(3 downto 0);sum:out std_logic;carry:out std_logic);
end component;
begin
r(0)<=x(0) and y(0);
c(1)<=x(0) and y(1);
c(2)<=x(1) and y(0);
c(3)<=x(0) and y(2);
c(4)<=x(1) and y(1);
c(5)<=x(2) and y(0);
c(6)<=x(0) and y(3);
c(7)<=x(1) and y(2);
c(8)<=x(2) and y(1);
c(9)<=x(3) and y(0);
c(10)<=x(1) and y(3);
c(11)<=x(2) and y(2);
c(12)<=x(3) and y(1);
c(13)<=x(2) and y(3);
c(14)<=x(3) and y(2);
c(15)<=x(3) and y(3);
a1:adder port map(c(1),c(2),r(1),d(0));
a2:adder port map(c(3),c(4),c(5),d(0),r(2),d(1));
a3:adder port map(c(6),c(7),c(8),c(9),d(1),r(3),d(2));
a4:adder port map(c(10),c(11),c(12),d(2),r(4),d(3));
a5:adder port map(c(13),c(14),d(3),r(5),d(4));
a6:adder port map(c(15),d(4),r(6),cout);
end behaviour;

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i have cleared many errors in the code but dont know the logic, so couldn't able to clear why the port map of adder mapped with four individual elements, but the actual adder requires a 3 bit vector and sum and carry out. i think the code is logically wrong. Any help?

 

[Er.abdulrehman]

First thing, Do you know why Port Map is used in the code???