Nexys 4 DDR External Hard Drive through USB port

[Sputnik12]

Hello,

I have run into a placer error when running block memory generator IPs in verilog, as I have too many ROM blocks for the nexys 4 DDR board. I would like to keep all my ROMs and therefore, was wondering if there are any tutorials anyone could guide me to for this? I have not been able to find what I have been looking for after googling for a few hours.

Any help would be much appreciated. Thanks.

 

[dpaul]

Could you please post the actual error?
Are those ROM blocks or BRAM blocks in the design?

 

[Sputnik12]

Could you please post the actual error?
Are those ROM blocks or BRAM blocks in the design?

Here is the error @dpaul.

 

[FvM]

Not clear what you want specifically to achieve. How's the problem related to external hard drive and USB?

 

[ads-ee]

The design requires more RAMB36/FIFO cells than are available in the target device. The design requires 1785 of such cell types but only 135 compatible sites are available in the target device.

This tells me you have 1785 ROMs (and/or RAMs) in your design.

Are all these ROMs you've created large ROMs, that require a 36Kbit size RAM block? If they are mostly that size you won't be able to implement this design in the device. If these ROMs are mostly small, then you might be able to create them as distributed ROM, see https://docs.xilinx.com/v/u/en-US/dist_mem_gen_ds322.

It seems to me the architecture of your design is not tailored to an FPGA.

 

[dpaul]

@Sputnik12
The error clearly states that either you need a larger FPGA or smaller RAMs.
So unless you us show/ or clearly describe why your design need such large amount of memory inside the FPGA fabric, there is little we can suggest.