Unwanted values in Result in VHDL

[Soh_bhat]

Hi there,
Good day. I am doing a simple mathematical operation using VIvado IP Floating point core. Also, I am getting the result. But as you can see, before getting the result, I am getting some unwanted values in the add & sub section. According to the operation, I will get 40400000 in the final result which is showing the waveform. But there are some unwanted values beforehand. Could you please tell me why this is so?
Thanks in advance.

 

[FvM]

Expect valid result after the specified latency.

Please show the core implementation with parameter settings. What is "add & sub section"? Internal core logic?

 

[Soh_bhat]

Behavioral:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity func1 is
    Port ( x_in : in STD_LOGIC_VECTOR(31 downto 0);
           y_in : in STD_LOGIC_VECTOR(31 downto 0);
           add1: inout STD_LOGIC_VECTOR(31 downto 0);
           sub1: inout STD_LOGIC_VECTOR(31 downto 0);
           f : inout STD_LOGIC_VECTOR(31 downto 0)
           );
end func1;

architecture Behavioral of func1 is
COMPONENT fpu_add
  PORT (
    aclk : IN STD_LOGIC;
    s_axis_a_tvalid : IN STD_LOGIC;
    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axis_b_tvalid : IN STD_LOGIC;
    s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axis_result_tready : IN STD_LOGIC;
    m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END COMPONENT;

COMPONENT fpu_sub
  PORT (
    aclk : IN STD_LOGIC;
    s_axis_a_tvalid : IN STD_LOGIC;
    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axis_b_tvalid : IN STD_LOGIC;
    s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axis_result_tready : IN STD_LOGIC;
    m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END COMPONENT;

COMPONENT fpu_mul
  PORT (
    aclk : IN STD_LOGIC;
    s_axis_a_tvalid : IN STD_LOGIC;
    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axis_b_tvalid : IN STD_LOGIC;
    s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axis_result_tready : IN STD_LOGIC;
    m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END COMPONENT;

signal aclk: std_logic;
signal s_axis_a_tvalid: std_logic := '0';
signal s_axis_b_tvalid: std_logic := '0';
signal s_axis_c_tvalid: std_logic := '0';
signal m_axis_result_tready: std_logic := '0';
constant clk_period : time := 10 ns;

begin
uut: fpu_add
  PORT MAP (
    aclk => aclk,
    s_axis_a_tvalid => s_axis_a_tvalid,
    s_axis_a_tdata => x_in,
    s_axis_b_tvalid => s_axis_b_tvalid,
    s_axis_b_tdata => y_in,
    m_axis_result_tready => m_axis_result_tready,
    m_axis_result_tdata => add1
  );


uut1: fpu_sub
  PORT MAP (
    aclk => aclk,
    s_axis_a_tvalid => s_axis_a_tvalid,
    s_axis_a_tdata => x_in,
    s_axis_b_tvalid => s_axis_b_tvalid,
    s_axis_b_tdata => y_in,
    m_axis_result_tready => m_axis_result_tready,
    m_axis_result_tdata => sub1
  );

uut2 : fpu_mul
  PORT MAP (
    aclk => aclk,
    s_axis_a_tvalid => s_axis_a_tvalid,
    s_axis_a_tdata => add1,
    s_axis_b_tvalid => s_axis_b_tvalid,
    s_axis_b_tdata => sub1,
    m_axis_result_tready => m_axis_result_tready,
    m_axis_result_tdata => f
  );
 

clk_process:  process
   begin
        aclk <= '0';
        wait for clk_period/2;
        aclk <= '1';
        wait for clk_period/2;
   end process;

end Behavioral;

Test bench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity func1_TB is
--  Port ( );
end func1_TB;

architecture Behavioral of func1_TB is
component func1 is
      Port ( x_in : in STD_LOGIC_VECTOR(31 downto 0) ;
           y_in : in STD_LOGIC_VECTOR(31 downto 0);
           add1: inout STD_LOGIC_VECTOR(31 downto 0);
           sub1: inout STD_LOGIC_VECTOR(31 downto 0);
           f : inout STD_LOGIC_VECTOR(31 downto 0)
           );
end component;

signal x_in: STD_LOGIC_VECTOR(31 DOWNTO 0) ;
signal y_in: STD_LOGIC_VECTOR(31 DOWNTO 0) ;
signal add1: STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0') ;
signal sub1 :STD_LOGIC_VECTOR(31 DOWNTO 0) ;
signal f:  STD_LOGIC_VECTOR(31 DOWNTO 0);
--signal clock: std_logic;
--constant clock_period : time := 100 ns;


begin
uut: func1 port map (
x_in => x_in,
y_in => y_in,
add1 => add1,
sub1 => sub1,
f => f );

--clk: process
--begin
--clock <= '0';
--  wait for clock_period/2;
--  clock <= '1';
--  wait for clock_period/2;
--   end process;

Fun: process
begin
     x_in <= x"40000000";  --2.0
       y_in <= x"3F800000";  --1.0
         wait for 10 ns;
     ---f -> 3.0 -> x"40400000"            
     
 
 
 
   
 end process;
 
 end Behavioral;

--- Updated Nov 13, 2022 ---

Yes the core logic. Add for addition of floating point and sub for the subtration. Mul for multiply. When I expand the hazy section in the output before the result, it is showing 23rd bit is 1 in the add section. I dont know how to set it to 0.

 

[FvM]

I don't understand the design. How are you operating xx_tvalid and xx_tready? Where is result f assigned? Expect tvalid to be set with new data and read the result with tready. Review IP manual about function of the handshake signals.

 

[Soh_bhat]

I have put tvalid as 0 and tdata is given as xin and yin in respective operations. F is generated from m_axis_tdata.
I am getting the output but before that there's some garbage signals. I don't know why is it coming? I am expecting the output 40400000 and it has come in the waveform. But you can see, there's some garbage signals beforehand. Why is it coming? My question is that.

Also, could you please share the manual link of the handshake signals. I have tried to get it from xilinx but couldn't find that way.

 

[FvM]

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