!! the phoenix law !!
Member level 1
Hello there !
I know there are some experts here and I think you certainly can help me with this
As the title said, I need help to design a two stage OTA for a typical LDO with 0.13um technology, I am using cadence for simulations,
By typical I mean that LDO stability is achieved by big off chip cap
This is my first trial and i just want a very regular design, however efficient as well
To be specific, I just need specs on the OTA (for the LDO)
So, based on your experience what specs should I follow ?
These are some specs, there might be others i should consider for LDO, If so please tell me, I have also estimated some values but I need someone to confirm
dc (Av)>=60db
unity gain bandwidth (GB)>=3M
input common mode range (Vin(min) and Vin(max))
load capacitance (CL) (from a PMOS pass element with upcox=1.12e-4 and Imax=1mA)
slew rate (SR)
settling time (Ts)
output voltage swing (Vout(max) and Vout(min))
power dissipation (Pdiss)
Moreover, The OTA should have NMOS mirror load (Input transistors for the first stage are PMOS not NMOS), to enhance PSRR
You might need also to know some info about the LDO itself
Output voltage=1.8v
Input voltage>=2
Output current<=1m
PSRR as high as possible
Any other specs like load regulation, line regulation, .. etc might be any reasonable value
Thanks in advance
Any help would be appreciated
I know there are some experts here and I think you certainly can help me with this
As the title said, I need help to design a two stage OTA for a typical LDO with 0.13um technology, I am using cadence for simulations,
By typical I mean that LDO stability is achieved by big off chip cap
This is my first trial and i just want a very regular design, however efficient as well
To be specific, I just need specs on the OTA (for the LDO)
So, based on your experience what specs should I follow ?
These are some specs, there might be others i should consider for LDO, If so please tell me, I have also estimated some values but I need someone to confirm
dc (Av)>=60db
unity gain bandwidth (GB)>=3M
input common mode range (Vin(min) and Vin(max))
load capacitance (CL) (from a PMOS pass element with upcox=1.12e-4 and Imax=1mA)
slew rate (SR)
settling time (Ts)
output voltage swing (Vout(max) and Vout(min))
power dissipation (Pdiss)
Moreover, The OTA should have NMOS mirror load (Input transistors for the first stage are PMOS not NMOS), to enhance PSRR
You might need also to know some info about the LDO itself
Output voltage=1.8v
Input voltage>=2
Output current<=1m
PSRR as high as possible
Any other specs like load regulation, line regulation, .. etc might be any reasonable value
Thanks in advance
Any help would be appreciated
Last edited: