timing problem in vhdl code

[ammassk]

dear all
I wrote a code for memory. I am getting correct values in the out put. but its not coming in correct clock period.Initially there are undefined values for many number of clock cycles.datas are also repeating for some clock cycles in the middle. how can i solve this?

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
USE ieee.numeric_std.ALL;

ENTITY read_rom IS
     port(clk: in std_logic;
				out1:out integer;
				out2:out integer
			);
END read_rom;

ARCHITECTURE beha OF read_rom IS 

type memory_array is array(integer range 0 to 3 , integer range 0 to 7)of character;
constant mem:memory_array:=("01011001","11100100","00100111","10011010");

type mem_arrayi is array (integer range 0 to 3,integer range 0 to 3) of integer;
signal data_i:mem_arrayi;

type mem_arrayj is array (integer range 0 to 3,integer range 0 to 3) of integer;
signal data_j:mem_arrayj;

begin
process(clk)
	 variable i:integer:=0;
	 variable j:integer:=0;
	 variable k:integer:=0;
	 variable l:integer:=0;
 begin 	  
		 if(clk='1' and clk'event)then			
		   if mem(j,i)='1' then
				data_i(k,l)<=i;
				data_j(k,l)<=j;
					l:=l+1;				 
				if l>3 then
					l:=0;
					k:=k+1;
                                     if(k>3) then
					   k:=0;
					-- else
				  end if;
			--	else				
				end if;			
                                         i:=i+1;
					 if(i>7) then
						   i:=0;
						 j:=j+1;
						if(j>3) then
						 j:=0;
							--  else							  
							end if;
						--else						
                             end if;			
				out1<=data_i(k,l);
                                out2<=data_j(k,l);	
		    else
				 i:=i+1;
				   if(i>7) then
						 i:=0;
						 j:=j+1;
					  if(j>3) then
						 j:=0;
					  else
					    null;
					  end if;
					 else
					     null;
					  end if;
			     end if;
	else
	         null;
		
            end if;			 
end process;
end beha;

 

[barry]

not sure, but you don't give a range to integer variables i,j, etc. (I would actually have expected an error here). Have you run a simulation of this?

Also, you might try adding an explicit reset to your process.

 

[TrickyDicky]

Right, a couple of points.

1. There is no need to have an else case with the clock.
2. why do you have an array of character, especially when its all '1' and '0'? this is probably not synthesisable. Why not an array of std_logic_vector?
3. You realise integers are 32 bit?
4. have you got a testbench? thats usually the best way to debug these problems. And this kind of problem is more for you to debug.

 

[barry]

Right, a couple of points.

1. There is no need to have an else case with the clock.
2. why do you have an array of character, especially when its all '1' and '0'? this is probably not synthesisable. Why not an array of std_logic_vector?
3. You realise integers are 32 bit?
4. have you got a testbench? thats usually the best way to debug these problems. And this kind of problem is more for you to debug.

I'm not even sure you can assign "01011001" to a character type. It looks like you should have gotten a lot of errors when you tried to compile this.

Like Tricky says, you should probably just use std_logic_vectors.

 

[ammassk]

I got the simulation result , but in actual clock.Also it gave undefined values for some clocks at the starting.How can i solve this?

- - - Updated - - -

I represented a 4 x 8 matrix having values 0 s and 1's in that array as characters. I didnt notice the integers are 32 bit. Thank you.

I got the test bench and it gives simulation rsult also. But not in actual clock. How can i solve this?

- - - Updated - - -

I didnt get any error when entered my matrix 4 x 8 like this. It takes each character in memory location correctly.