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they are different kinds of spef (standard parasitic extraction file) which are extracted by the tool like QRC for post rounting timing analysis for setup and hold violations.
We back annotate these exacted files for timing closure.
r,rc worst and best are used to mimic better process variation of parasitic C and R in .13nm and below additionaly to slow,slow and fast,fast transitor variation in the simulation. Motivation is to get better yield.
thank you. rcworst gives worst [max]delay, yes? rcbest gives best [min] delay yes? so this give max and min timing... why run cworst, cbest/ wat dos this tel us.
There is no clear relationship between RC corners and maximum delay. Some nets are resistance-dominated and some are capacitance-dominated and some are a mix. Add to that the fact that increasing delay is bad for setup timing but good for hold timing, and vice-versa for decreasing delay.
So all you can say is that by picking different R and C combinations you will get a different delay picture for your circuit. Not necessarily better or worse, just different.
Foundries try to restrict the number of corners people need to verify, so they pick two corners that are typically best and worst. Just keep in mind it is a simplification of what really happens.
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