synchronous vs asynchronous

[anoop12]

Hi,
can anyone differentiate between synchronous and asynchronous signals in terms of VHDL
regards

 

[suru]

if clk is used then synchronous otherwise asynchronous.

if clk'event and clk='1' then
y<= x;
z<=k;

;;;;synchronous.

 

[gck]

Signals controlled by the clock event is called as synchronous.


If the internal signal driven by the other signal which comes under the clock then first signal will also became the synchronous

 

[vlsi_freak]

Hi.

Synchronous reset in VHDL.

if (clk'event and clk='1') then
if reset = '1' then
---
elsif
-----
end if;
end if;

Asynchronous reset in VHDL

if reset='1' then
-------
elsif clk'event and clk='1' then
---------
end if;

Hope it helps

Thanks

 

[darylz]

the important thing is not the difference between sync and async signals.... are preparing an interview?