Digit0001
Member level 1
Hi
Can someone help me on how would you code the following:
A synchronous 4 bit counter up performs the counting and the loading on the falling edge of the clock. The clear is an asynchronous input which resets the counter. The counter generates a carry Cout in state 15 if T = '1'. The counter increments if P and T = 1.
This is what i have done. Can someone tell me if this is correct?
P.S
Can someone help me on how would you code the following:
A synchronous 4 bit counter up performs the counting and the loading on the falling edge of the clock. The clear is an asynchronous input which resets the counter. The counter generates a carry Cout in state 15 if T = '1'. The counter increments if P and T = 1.
This is what i have done. Can someone tell me if this is correct?
Code:
entity ques4 is
port(P,T : in std_logic;
Clear,Load : in std_logic;
Clk : in std_logic;
cout : in std_logic;
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0));
end ques4;
architecture Behavioral of ques4 is
signal count : std_logic_vector(3 downto 0);
begin
process(clk,clear)
begin
if(clear = '0') then
count <= "0000";
elsif(clk'event and clk='0') then
if(load = '1') then
count <= D;
elsif(T = '1') then
count <= D;
elsif(T='1' and P='1') then
count <= count + "0001";
end if;
end if;
end process;
Q <= count;
end Behavioral;
P.S