3 bit dual mode counter in Verilog

[Gray Rosewood]

Greetings, I need guidance to code a question with the requirements listed on the following:
Design a 3-bit dual mode counter that counts
(i) even number in increment order when select=1;
(ii) odd number in decrement order when select=0;
Apart from input select, the counter has a synchronous active-high reset and it is a negative edge triggered synchronous counter.


Attached is the code that has been worked on and the corresponding University program waveform output.

module updown_synccounter (CLK, reset, select, out);// counter has a synchronous
input CLK, reset, select; //active-high reset and it is a negative edge triggered synchronous counter.
output reg [2:0] out;

always@ (negedge CLK)
begin
         if (reset==1'b1)
            out <=3'b000;
            
            else if (select==1)
            out <= out+1;
            
            else
            out <= out-1;
            
end
endmodule

 

[barry]

I don't know what "even number in increment order" or "odd number in decrement order" mean.

Your code is for a simple up-down counter. Your simulation, however, makes no sense. You've got reset and select toggling constantly, at a faster rate than the clock. What are you trying to do?

 

[nand_gates]

May be this is what you are looking for ...

// counter has a synchronous
//active-high reset and it is a negative edge triggered synchronous counter.
module updown_synccounter (clk, reset, select, out);
   input clk, reset, select;
   output [2:0] out;
   reg [1:0]    count;
   assign out = {count,~select};
  
always@ (negedge clk)
  begin
     if (reset==1'b1)
       count <= {2{~select}};
     else if (select==1)
       count <= count+1;
     else
       count <= count-1;
  end
endmodule // updown_synccounter

module test();
   reg clk;     
   reg reset;   
   reg select; 
   wire [2:0] out;

   updown_synccounter updown_synccounter(.out    (out[2:0]),
                                         .clk    (clk),
                                         .reset  (reset),
                                         .select (select));
   initial begin
      clk = 1'b0;
      reset = 1'b1;
      select = 1'b1; // count up even
      repeat(3) @(posedge clk);
      reset = 1'b0; //start counting
      repeat(20) @(posedge clk);
      reset = 1'b1;
      select = 1'b0; // count down odd
      repeat(1) @(posedge clk);
      reset = 1'b0;
      repeat(20) @(posedge clk);
      $finish();
   end // initial begin
   always #5 clk = ~clk;
endmodule // test

 

[danadakk]

Should you not increment the counter by 2 here, rather than the +1 you show ? -

     else if (select==1)
       count <= count+1;

Regards, Dana.

 

[danadakk]

One thought is should you test the counter, if told to count up by even count,
implied is the counter value should be even before you increment....? Maybe test the
value to either round up, or down, then do the even increment / decrement ? Or is
that reading into the problem more than is necessary ....?


Regards, Dana.