Andrei Salahoru
Newbie level 5
Hi,
There are two signals who must be taken in account. First is the status signal, and then is a N ms period signal, wich will increment a module later.
Now, every time the status is active, I have to check the local clock accuracy (?) according to N ms signal and synchronize the N ms signal to internal clock.
But when the status is low, I have to generate myself an N ms signal. This generated N ms signal will replace the external signal.
Does anyone has an idea how this module must be modeled?
And if the status signal is asynchronious, how do I keep in track how many ms are left untill the next rising edge? ( when the internal signal will replace the external, it has to be exactly at the same time. Also, the viceversa must be the same)
I will develop in Verilog, but the thing I want is the idea.
If I didn't explain well, please let me know.
Best regards,
Andrei Salahoru.
There are two signals who must be taken in account. First is the status signal, and then is a N ms period signal, wich will increment a module later.
Now, every time the status is active, I have to check the local clock accuracy (?) according to N ms signal and synchronize the N ms signal to internal clock.
But when the status is low, I have to generate myself an N ms signal. This generated N ms signal will replace the external signal.
Does anyone has an idea how this module must be modeled?
And if the status signal is asynchronious, how do I keep in track how many ms are left untill the next rising edge? ( when the internal signal will replace the external, it has to be exactly at the same time. Also, the viceversa must be the same)
I will develop in Verilog, but the thing I want is the idea.
If I didn't explain well, please let me know.
Best regards,
Andrei Salahoru.