suggestion for my vlsi+dip project

[manoranjan sb]

Hi
I am undertaking a project named "A VLSI architecture for image registration" an IEEE 2007 paper. Please suggest me some ideas to design the hardwares involved in that paper such as Address and control signal generator unit, Data fixer unit, window processor.

 

[amitjagtap]

Is it your final project or you are doing it in your company.....

 

[manoranjan sb]

I am a final year electronics and communication engineering student. My project title is 'A VLSI architecture for image registration' an IEEE 2007 paper. Can anyone please suggest me how to design the various blocks in that architecture. If anyone wants I am ready to send the softcopy of that paper.

 

[amitjagtap]

Hi Manoranjan
I think this project will be very big as your final year project. While working alone it will be difficult to design even a single block with required specifications. Do you want to design this from transistor level?
Well what i suggest is take some small module...start with transistor level design and take it up to tape out...While doing this you will go through all VLSI design steps and those are really great to learn.

 

[manoranjan sb]

Which coding would be better for the my project? I have got trained already with verilog. whether i can follow verilog or vhdl for implementation.

 

[manoranjan sb]

Is it possible to convert all the matlab files to vhdl/verilog file using any inbuilt functions in matlab??