BlackOps
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vhdl code for sr flip flop
Hello,
i am trying to build VGA controller. it will have 2 10 bit up counters and 4 flip flops. i already have a schematic of it.
now i want to write down complete VHDL structural code for my SR flip flop, please take a look at the image of the flip flop which i need inside my controller.
as i see from the Enoch's book, SR flip flop is just modified D flip flop, please take a look at the second pic.
now, i need to modify VHDL code for SR flip flop, but i also need to include asynchronous clear signal, as shown on the first pic,...for the VGA controller..
here is my code:
i compiled it in Modelsim, it gave me errors, but i dont understand them good...can u take a look and say what could be wrong?
can u say me is it normally designed SR flip flop model?
and one more thing... in my VGA controller from the Enoch's book, i will have 4 of such flip flops... do i have to write them all down in structural code in one source VHD file??? or can i write down one structural code for this flip flop and use it in my main controller source file? if yes then how?
can i write down just behavioral code for this flip flop? will it work if i will want to create this controller on XUPV2P virtex2 board? or i need only structural?
(anyway i think structural is more complete)
[/code]
Hello,
i am trying to build VGA controller. it will have 2 10 bit up counters and 4 flip flops. i already have a schematic of it.
now i want to write down complete VHDL structural code for my SR flip flop, please take a look at the image of the flip flop which i need inside my controller.
as i see from the Enoch's book, SR flip flop is just modified D flip flop, please take a look at the second pic.
now, i need to modify VHDL code for SR flip flop, but i also need to include asynchronous clear signal, as shown on the first pic,...for the VGA controller..
here is my code:
Code:
-- define the operation of the 2-input NAND gate
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_2 IS PORT (
I0, I1: IN STD_LOGIC;
O: OUT STD_LOGIC);
END NAND_2;
ARCHITECTURE Dataflow_NAND2 OF NAND_2 IS
BEGIN
O <= I0 NAND I1;
END Dataflow_NAND2;
-- define the operation of the 3-input NAND gate
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_3 IS PORT (
I0, I1, I2: IN STD_LOGIC;
O: OUT STD_LOGIC);
END NAND_3;
ARCHITECTURE Dataflow_NAND3 OF NAND_3 IS
BEGIN
O <= NOT (I0 AND I1 AND I2);
END Dataflow_NAND3;
-- define the operation of the SR input block to the D flip-flop
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SRin IS PORT (
R, S, Q: IN STD_LOGIC;
D: OUT STD_LOGIC);
END SRin;
ARCHITECTURE Dataflow_SRin OF SRin IS
BEGIN
D <= (Q AND (NOT R)) OR S ;
END Dataflow_SRin;
-- define the structural operation of the SR latch
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SRlatch IS PORT (
SN, RN: IN STD_LOGIC;
Q, QN: BUFFER STD_LOGIC);
END SRlatch;
ARCHITECTURE Structural_SRlatch OF SRlatch IS
COMPONENT NAND_2 PORT (
I0, I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1: NAND_2 PORT MAP (SN, QN, Q);
U2: NAND_2 PORT MAP (Q, RN, QN);
END Structural_SRlatch;
-- define the structural operation of the SR flip-flop
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SR-FF IS PORT (
S, R, Clear, Clock: IN STD_LOGIC;
Q : BUFFER STD_LOGIC);
END SR-FF;
ARCHITECTURE Structural_SR-FF OF SR-FF IS
SIGNAL N1, N2, N3, N4, N5: STD_LOGIC;
COMPONENT SRlatch PORT (
SN, RN: IN STD_LOGIC;
Q, QN: BUFFER STD_LOGIC);
END COMPONENT;
COMPONENT NAND_2 PORT (
I0, I1: IN STD_LOGIC;
O: OUT STD_LOGIC);
END COMPONENT;
COMPONENT NAND_3 PORT (
I0, I1, I2: IN STD_LOGIC;
O: OUT STD_LOGIC);
END COMPONENT;
COMPONENT SRin PORT (
S, R, Q: IN STD_LOGIC;
D: OUT STD_LOGIC);
END COMPONENT
BEGIN
U1: SRlatch PORT MAP (N4, Clock, N1, N2, Clear); -- set latch
U2: SRlatch PORT MAP (N2, N3, Q, QN, Clear); -- output latch
U3: NAND_3 PORT MAP (N2, Clock, N4, N3); -- reset latch
U4: NAND_2 PORT MAP (N3, N5, N4, Clear); -- reset latch
U5: SRin PORT MAP (S, R, Q, N5); -- SR INPUT
END StructuralDFF;
i compiled it in Modelsim, it gave me errors, but i dont understand them good...can u take a look and say what could be wrong?
can u say me is it normally designed SR flip flop model?
and one more thing... in my VGA controller from the Enoch's book, i will have 4 of such flip flops... do i have to write them all down in structural code in one source VHD file??? or can i write down one structural code for this flip flop and use it in my main controller source file? if yes then how?
can i write down just behavioral code for this flip flop? will it work if i will want to create this controller on XUPV2P virtex2 board? or i need only structural?
(anyway i think structural is more complete)
[/code]