[SOLVED] String signal on testbench

[nsgil85]

Hi everyone

I have a UUT which include bunch of states, (each state is numbered).
Without using "assert" Is there a posible way, on Test bench to translate those numbers into string signals so it can be readable


Thanks
Gil

 

[FvM]

Aren't VHDL or System Verilog enumeration types decoded by your simulator?

 

[TrickyDicky]

All types can easily be converted to strings. Post some code explaining what you're trying to do.

 

[K-J]

Hi everyone

I have a UUT which include bunch of states, (each state is numbered).
Without using "assert" Is there a posible way, on Test bench to translate those numbers into string signals so it can be readable


Thanks
Gil

The 'report' statement is what you would use. While 'report' is typically part of an assert, it can standalone as well. The only drawback there is that report on it's own must be used within a process while assert can be concurrent. As for converting the state to a text string, you would write a function that takes as input the custom type that defines your state, and returns a string.

function to_string(st:  my_state) return string is
begin
   case st is
      when x1 =>  return("X1");
      when x2 =>  return("X2");
      ...
   end case;
end function to_string;
...
process
begin
   report "State=" & to_string(st);
end process;

Kevin Jennings

 

[nsgil85]

Thanks for reply,

I manged to compile the code below with success of simulation

---

Code VHDL - [expand]
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type states_of_driver is
(
    ST_A ,  
    ST_B ,      
    ST_C ,          
    ST_D ,      
    ST_E ,      
    ST_F ,          
    ST_G
) ;
 
signal sig_states_of_driver     : states_of_driver ;
 
 
 
driver_modes:
process
begin
                wait until rising_edge(simulation_G_CLK);
                sig_states_of_driver <=     ST_A    when simulation_PORT_FLAG_STAT = 0  else
                                    ST_B    when simulation_PORT_FLAG_STAT = 1  else 
                                    ST_C    when simulation_PORT_FLAG_STAT = 2  else
                                    ST_D    when simulation_PORT_FLAG_STAT = 3  else
                                    ST_E            when simulation_PORT_FLAG_STAT = 4  else
                                    ST_F    when simulation_PORT_FLAG_STAT = 5  else
                                    ST_G    when simulation_PORT_FLAG_STAT = 6 ;
 
end process driver_modes;

---

 

[TrickyDicky]

this code might be a little tidier:

sig_states_of_driver <= states_of_driver'val(simulation_PORT_FLAG_STAT);

It is:
VHDL 87/93/2002 compatible
Doesnt have to be modified when more states are added.

Your current code will only work in VHDL 2008

 

[nsgil85]

Worked great!

i've changed the "wait until rising_edge(simulation_G_CLK);" line to "wait until simulation_PORT_FLAG_STAT'event ;" for asynchronous update

Great guys