SPI interface - problem with parallel to serial converter (verilog)

[Araxnid]

Hello everyone.

I was working with spi module and encoutered some problem -
My code - SPI module(it's not finished yet):

module ParallelToSerial(
    input CLK,
    input [15:0]par_INPUT,
	 input enable,
    output ser_OUTPUT,
	 output SCLK,
	 output CS
    );

reg [15:0]load;
reg [6:0]counter;

assign ser_OTPUT=load[0];
assign SCLK=CLK;
assign CS = enable;

always @(negedge enable) begin
	load=par_INPUT;
end

always @(posedge CLK) begin
	if (enable==1'b0) begin
		load=load[0] & load[15:1];
	end
end
endmodule

and my top_module file:

module top_module(
    input CLK,
    output MOSI,
	 input test_signal,
    output SCLK,
	 output CS
    );

reg enable = 1'b1;
reg par_INPUT = 16'd3054;

always @(posedge CLK) begin
	if (test_signal==1'b1) begin
		enable = 1'b0;
	end
end

ParallelToSerial	u1(.CLK(CLK),.par_INPUT(par_INPUT),.enable(enable),.ser_OUTPUT(MOSI),.SCLK(SCLK),.CS(CS));

endmodule

So, XILINX ISE saying me that:
WARNING:Xst:1305 - Output <ser_OUTPUT> is never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <ser_OTPUT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <counter> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <par_INPUT> is used but never assigned. This sourceless signal will be automatically connected to value 0.

I cant understand why its thinking that ser_OUTPUT is never assigned? Its assigned to load, and load shifts every clk cycle.... test_signal is special signal from my board which will pull down CS and activate SPI module. Can anyone explain what im doing wrong with this? Thanks.

 

[mail4idle2]

You have made a typo mistake on 13th line of ParallelToSerial code file
assign ser_OTPUT=load[0];

It has to be
assign ser_OUTPUT=load[0];

 

[Araxnid]

You have made a typo mistake on 13th line of ParallelToSerial code file
assign ser_OTPUT=load[0];

It has to be
assign ser_OUTPUT=load[0];

Sorry, but i cant find any differences..

 

[joelby]

Did changing "OTPUT" to "OUTPUT" resolve the warning about ser_OTPUT being assigned but not used? To avoid typos like this, I recommend using "`default_nettype none" at the start of every Verilog file you create.

Your use of "negedge enable" as a clock is bad design practice. In this sort of design, everything should be synchronous to a single clock (and a single clock edge). You'll probably need to use a state machine for this design, too.

 

[Araxnid]

Did changing "OTPUT" to "OUTPUT" resolve the warning about ser_OTPUT being assigned but not used? To avoid typos like this, I recommend using "`default_nettype none" at the start of every Verilog file you create.

Your use of "negedge enable" as a clock is bad design practice. In this sort of design, everything should be synchronous to a single clock (and a single clock edge). You'll probably need to use a state machine for this design, too.

Oooh, i didnt notice difference between OTPUT and OUTPUT, thanks!!

And yes, now i think its bad idea to use nededge in design, thanks again!