praneshcn
Member level 5
Hi,
when we have an external clock source and an PLL inside a chip level design from which point to which point will source latency be considered. As it is a chip level design consider the clock pad in between the external clock source and PLL.
when we have an external clock source and an PLL inside a chip level design from which point to which point will source latency be considered. As it is a chip level design consider the clock pad in between the external clock source and PLL.