koce
Newbie level 3
how to delay the signal?
Hi everyone,
I use Altera MAXII CPLD for my project. I program it using Quartus II software and VHDL language. With CPLD I control switches using one global clock signal. For one switch, I want to turn it on not on the rising edge of the global clock but to delay the turning on (10ns for example).
In my VHDL code I use generic type of data.
generic (Tdelay: time:=10ns); I use this constant when I want to delay my signal:
when (clock'event and clock='1')
s1='1' after Tdelay;
VHDL syntax verification is OK but I have a problem when I want to do final compilation.
The error is something like type time does not match string literal
I thing that it is because I use generic type of data.
If someone know the other way of delayin signal using VHDL code please share with me. You will help me a lot!
Thanks
Bojan
Hi everyone,
I use Altera MAXII CPLD for my project. I program it using Quartus II software and VHDL language. With CPLD I control switches using one global clock signal. For one switch, I want to turn it on not on the rising edge of the global clock but to delay the turning on (10ns for example).
In my VHDL code I use generic type of data.
generic (Tdelay: time:=10ns); I use this constant when I want to delay my signal:
when (clock'event and clock='1')
s1='1' after Tdelay;
VHDL syntax verification is OK but I have a problem when I want to do final compilation.
The error is something like type time does not match string literal
I thing that it is because I use generic type of data.
If someone know the other way of delayin signal using VHDL code please share with me. You will help me a lot!
Thanks
Bojan