ishould
Newbie level 4
I'm not sure if this is where I'm supposed to post this, but here it is anyway. This'll probably be really easy
"Consider a NAND gate with NMOS and PMOS sizes of .5um/.25um and .75um/.25um respectively" They go on to say that they're sized this way to make the resistances equal, and the rise and fall times are approximately equal in a worst-case scenario. When I calculate the effective resistances however, they aren't nearly the same, so I'm obviously doing it wrong. I thought PMOS has to have ~3x the width of the NMOS, and in this case it's only 1.5x.
Can someone explain it to me?
-ishould
"Consider a NAND gate with NMOS and PMOS sizes of .5um/.25um and .75um/.25um respectively" They go on to say that they're sized this way to make the resistances equal, and the rise and fall times are approximately equal in a worst-case scenario. When I calculate the effective resistances however, they aren't nearly the same, so I'm obviously doing it wrong. I thought PMOS has to have ~3x the width of the NMOS, and in this case it's only 1.5x.
Can someone explain it to me?
-ishould