Mkanimozhi
Full Member level 4
Hi friends,
How to display the simtulation time in VHDL test bench any specific method or fucntion is there like we have in verilog.
Thanks and regards,
Kanimozhi.M
How to display the simtulation time in VHDL test bench any specific method or fucntion is there like we have in verilog.
Thanks and regards,
Kanimozhi.M