MSAKARIM
Full Member level 3
When i simulated this code of 8-bit adder i get output"UUUUUUUU" when using "carry" as a signal instead of variable. i want to know what is the problem ?
Code:
entity adder8 is
port(a,b: in std_logic_vector(7 downto 0);
cin:in std_logic;
sum: out std_logic_vector( 7 downto 0);
co: out std_logic);
end adder8;
architecture Behavioral of adder8 is
signal carry:std_logic_vector(8 downto 0);
begin
process(a,b,cin)
begin
carry(0)<=cin;
G1:for i in 0 to 7 loop
sum(i) <= a(i) xor b(i) xor carry(i);
carry(i+1)<= (a(i) and b(i)) or (a(i) and carry(i)) or (b(i) and carry(i));
end loop;
co<=carry(8);
end process;
end Behavioral;