Richard29
Member level 1
Hi all,
I am really stuck now. The following module is working fine in simulation but does not work properly in hardware. It is so simple, but I can't figure out why it is not working. Essentially, this module gets two input operands (op1, op2), two comand signals (fu_op, fu_imm) and a clock. The following two evaluations
are executed in consecutive clock cycles:
S0 (x) tx <= x;
r <= just some simple xor, or, and with input x
F0(tx, x, y) r <= just some simple xor, or, and with input x, y and also tx!
I guess that somehow the passing of tx to F0 is not working. Is there anything wrong how I try to handle the case of tx, might I have forgotten it in the sensitivity list?
Many thanks for your input!
I am really stuck now. The following module is working fine in simulation but does not work properly in hardware. It is so simple, but I can't figure out why it is not working. Essentially, this module gets two input operands (op1, op2), two comand signals (fu_op, fu_imm) and a clock. The following two evaluations
are executed in consecutive clock cycles:
S0 (x) tx <= x;
r <= just some simple xor, or, and with input x
F0(tx, x, y) r <= just some simple xor, or, and with input x, y and also tx!
I guess that somehow the passing of tx to F0 is not working. Is there anything wrong how I try to handle the case of tx, might I have forgotten it in the sensitivity list?
Many thanks for your input!
Code:
entity test_module is
port
(
op1 : in std_logic_vector(31 downto 0); -- First input operand
op2 : in std_logic_vector(31 downto 0); -- Second input operand
fu_op : fu_op_type; -- Opcode
fu_imm : in std_logic_vector(7 downto 0); -- Immediate
clk : in std_logic; -- clock
res : out std_logic_vector(31 downto 0) -- Result
);
end;
architecture rtl of test_module is
type res_sel_type is (PASS, S0, F0);
signal res_sel : res_sel_type;
signal load : std_logic := '0';
signal tx : std_logic_vector(31 downto 0) := (others => '0');
procedure S0_proc
(
signal a : in std_logic_vector(31 downto 0);
signal r : out std_logic_vector(31 downto 0)
)
is
constant Z : std_logic_vector(31 downto 0) := (others => '0');
variable res : std_logic_vector(31 downto 0);
begin
r := ( a(6 downto 0) & a(31 downto 7) ) xor ( a(17 downto 0) & a(31 downto 18) ) xor ( Z(2 downto 0) & a(31 downto 3) );
end;
procedure F0_proc
(
signal a : in std_logic_vector(31 downto 0);
signal b : in std_logic_vector(31 downto 0);
signal c : in std_logic_vector(31 downto 0);
signal r : out std_logic_vector(31 downto 0)
)
is
variable res : std_logic_vector(31 downto 0);
begin
r <= ( a and b ) or ( ( a or b ) and c ) ;
end;
begin
-- Decode opcode
dec_op: process (fu_op, fu_imm)
variable tmp : res_sel_type;
variable ld : std_logic;
begin
-- Default value
tmp := PASS;
ld := '0';
if (fu_op = FU_FPGA) then
case fu_imm is
-- compute S0, store first operand
when S0 =>
ld := '1';
tmp := S0;
-- compute F0
when F0 =>
ld := '0';
tmp := F0;
when others =>
-- Leave default values
end case;
res_sel <= tmp;
load <= ld;
end if;
end process;
-- Selection of output
sel_out: process (res_sel, op1, op2)
begin
case res_sel is
when S0 =>
S0_proc(op1, res);
when F0 =>
F0_proc(tx, op1, op2, res);
end case;
end process;
sync: process(clk)
begin
if clk'event and clk = '1' then
if load = '1' then
tx <= op1;
end if;
end if;
end process;
end rtl;
Last edited:
