Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
Umm.. according to my little understanding, signals get updated at the end of a process.
So if at end of Proc0 value of F is say 1, then when proc1 runs its can change he value of F to 0 if it wills.
Or is it that processes will run at the same time?! I am confused because we don't have a clock!
The process is entered when the signals in the sensitivity list change. Only if A/B and C/D have inputs that change at the same time will both proc0 and proc1 run in parallel.
If the inputs for A/B change and C/D stay the same then proc0 will be entered and if the result of proc0's AND gate is inverted from the output of proc1 then you'll end up with an X in simulation and a problem with synthesis as you've shorted two outputs together. If the two procs drive their outputs to the same value then the result will be 0 or 1.
If such a thing was done on a physical PCB you would end up burning up one or both parts (AND gate, OR gate) output driver. As VHDL is trying to simulate what can be done in hardware, this is not allowed an will result in X's in simulation and probably an error in most synthesis tools.
You definitely need to keep in mind VHDL is meant to describe hardware.
No proc1 is assigning that output to the opposite value from proc0 CONTINUOUSLY until changed. You are thinking like a software engineer where assigning a variable occurs at that line of code and any other lines of code that assign something to the same variable don't affect the line of code being executed.Question: You mentioned that the process is entered when the inputs change. So if A/B change but C/D stay the same, as you say, then proc1 should not run at all. And "if the result of proc0's AND gate is inverted from the output of proc1 then you'll end up with an X" won't happen. Am I correct?
If you want to produce a hardware design, then yes. I'm sure there are some mutually exclusive cases where you might be able to abuse VHDL and implement two processes that drive the same signal, but if you insist on coding like that, then IMO you should not go into FPGA/ASIC design and stick with software.Is this explanation valid: "When we have two processes running under the same architecture then both of them cannot update the same signal"?
- - - Updated - - -
Is this explanation valid: "When we have two processes running under the same architecture then both of them cannot update the same signal"?