priya23
Newbie level 2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vari is
port(a,b,c:in integer;
d,eut integer);
end vari;
architecture df of vari is
signal j:integer:=0;
begin
j<=j+2;
e<=j;
process(a)
variable k:integer:=0;
begin
k:=k+1;
d<=k;
end process;
end architecture;
hre i check e value....
so in my first run of simulation e=9996,j=9998.hw the j is 9998.i declare initially j as zero.then hw j is showing 9998.actually j must be 1 at the time of simulation.anyone knw abt this pls rply
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vari is
port(a,b,c:in integer;
d,eut integer);
end vari;
architecture df of vari is
signal j:integer:=0;
begin
j<=j+2;
e<=j;
process(a)
variable k:integer:=0;
begin
k:=k+1;
d<=k;
end process;
end architecture;
hre i check e value....
so in my first run of simulation e=9996,j=9998.hw the j is 9998.i declare initially j as zero.then hw j is showing 9998.actually j must be 1 at the time of simulation.anyone knw abt this pls rply